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MT90503 2048VC AAL1 SAR
Data Sheet Features
* AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services Interoperability Specifications" (Nx64 Basic Service, DS1 Nx64 Service with CAS, and E1 Nx64 Service with CAS) Two UTOPIA ports (Level 2, 16-bit, 50 MHz) with loopback function for dual fibre ring applications Third UTOPIA port for connection to an external AAL5 SAR processor, or for chaining multiple MT90503 or other SAR or IMA devices Flexible aggregation capabilities (Nx64) to allow any combination of 64 Kbps TDM bus provides 32 bidirectional serial TDM streams at 2.048, 4.096, or 8.192 Mbps for up to 4096 TDM 64 Kbps channels Compatible with H.100 and H.110 interfaces Ordering Information MT90503AG 503 Pin PBGA
December 2004
*
For temperature range, see page 207.
* *
TDM to ATM transmission latency less than 250 s Support for clock recovery - Adaptive Clock Recovery, Synchronous Residual Time Stamp (SRTS) or external Support master and slave TDM bus clock operation 8- or 16-bit microprocessor port, configurable to Motorola or Intel timing Master clock rate up to 80 MHz Single power supply device (3.3V) IEEE 1149 (JTAG) interface
* *
* * * * *
* *
*
Control Memory (external SSRAM)
Address bus and 8- or 16-bit Data bus
Control Memory Controller
CPU Module
Registers H.100/ H.110 TDM Bus 4096 x 64kbps TX_SAR Module RX_SAR Module
UTOPIA Module Port A Port B RXA Port TXA Port RXB Port TXB Port RXC Port TXC Port
TDM Module
Data Memory Controller Clock Recovery Submodule
Port C
Boundary Scan Logic JTAG Interface
Clock Signals Data Memory (external SSRAM)
Figure 1 - Functionl Block Diagram 1
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MT90503
Description
Data Sheet
The MT90503 is an AAL1 SAR, which offers a highly integrated solution for interfacing telecom bus-based systems with ATM networks. The device has the capability of simultaneously processing 2048 bidirectional channels of 64 kbps. The MT90503 can be connected directly to an H.100 or H.110 compatible bus. The device also offers the capability of using Channel Associated Signalling (CAS) to support Circuit Emulation Service (CES) for Structured Data Transfer (SDT). The interface to the TDM port is provided by a TDM bus, which consists of 32 bidirectional serial TDM data streams at 2.048, 4.096, or 8.192 Mbps, therefore allowing for 2048 bidirectional TDM channels operating at 64 kbps. This TDM bus is compatible with the ECTF H.100 and H.110 specifications. The interface to the ATM domain is provided by three UTOPIA ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Port A can also be configured as Level 2 M-PHY mode.
Applications
* * * * * * * * ATM Access and Multiplexing Equipment Switching Platforms that provide internetworking between TDM and ATM ATM Edge Switches ATM uplink for expansion of COs, PBXs, or open switching platforms using an adjunct ATM switch Integrated Digital Loop Carrier (IDLC) SONET or SDH Add and Drop Multiplexers (ADM) Next Generation Digital Loup Carrier (NGDIC) Digital Subscriber Line Access Multiplexer DSLAM with Gateway
Switching Feature
* Cells coming in from any of the UTOPIA ports can be switched to any other port. The user has the option to change the VPI and VCI fields.
PURCHASE OF THIS PRODUCT DOES NOT GRANT THE PURCHASER ANY RIGHTS UNDER PATENT NO. 5,260,978. USE OF THIS PRODUCT OR ITS RE-SALE AS A COMPONENT OF ANOTHER PRODUCT MAY REQUIRE A LICENSE UNDER THE PATENT WHICH IS AVAILABLE FROM TELCORDIA TECHNOLOGIES, INC., 445 SOUTH STREET , MORRISTOWN, NEW JERSEY 07960.
ZARLINK ASSUMES NO RESPONSIBILITY OR LIABILITY THAT MAY RESULT FROM ITS CUSTOMERS' USE OF ZARLINK PRODUCTS WITH RESPECT TO THIS PATENT. IN PARTICULAR, ZARLINK'S PATENT INDEMNITY IN ITS TERMS AND CONDITIONS OF SALES WHICH ARE SET OUT IN ITS SALES ACKNOWLEDGEMENTS AND INVOICES DOES NOT APPLY TO THIS PATENT.
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MT90503
Data Sheet
PSTN SDT Traffic T3/E3 T3/E3 LIU M13 MUX Octal T1/E1 Framers MT9072
2048 channels
AALI SAR
MT90503
Clock Oscillator
Digital PLL MT9045
ATM UTOPIA Bus
ATM Network Uplink OC-12 Framers & ATM Cell Access
Stratum 3 Timing Card PSTN UDT Traffic T1/E1 Circuit Emulation Services T1/E1 LIU
28 port
AAL1 SAR
MT90528
Optical Interface & Drivers
Stratum 3 Timing Card Clock Oscillator Digital PLL MT9045
Traffic Management & Switching ATM Traffic T1/E1 IMA Uplink T1/E1 Framers MT9076 Octal/IMA
MT90220
Figure 2 - ATM Switch Application
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MT90503 Table of Contents
Data Sheet
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 Functional Overview of the MT90503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.0 Features Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 ATM SAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 Required External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 Particular Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.0 Pin Designations and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.1 CPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.1 Example Interrupt Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.2 Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.3 Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.2 Intel/Motorola Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.2.1 Extended Indirect Accessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.2 Extended Indirect Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.3 Extended Indirect Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.4 Extended Direct Accessing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.5 Extended Direct Writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.2.6 Extended Direct Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.3 MT90503 Reset Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 TDM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.1 TDM Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.2 TDM Bus Clocking Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.3 TDM Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.4 TDM Channel Association Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.4.1 Non CAS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.4.2 CAS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.5 TDM Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.6 TDM Circular Buffer Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.6.1 Non-multiframing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.6.2 E1/T1 Multiframing (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 TX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.1.1 Support and Trunking for Different Types of ATM Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.2 TX_SAR Event Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.2 The Transmit Event Scheduler Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.3 Transmit Event Scheduler Fields Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.2.4 Scheduler Events Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2.5 Bandwidth Limitations for Transmit Scheduler Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.3 Out of Bandwidth Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.3.1 Percent of Bandwidth Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3.2 Distribution of Events by Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.4 Mapping of the Transmit Event Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.5 TX_SAR Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.5.1 TX_SAR Control Structure Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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Zarlink Semiconductor Inc.
MT90503 Table of Contents
Data Sheet
4.3.6 Miscellaneous TX_SAR Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.6.1 T1 with CAS and E1 with CAS Cell Format Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.6.2 Support of Partially-Filled Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.6.3 TX_SAR FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 RX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.1 Treatment of Data Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.2 Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.3 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.4 Error Report Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5 UTOPIA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.2 UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.3 Errors on received cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.4 Transmit and Receive State Machines for ATM and PHY Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.5 Cell Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.6 Match & Mask for cell routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.6.1 Look-Up Tables Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.6.2 LUT Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.6.3 UTOPIA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.7 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.8 UTOPIA Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.5.9 External Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6 Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.1 Two Point Generation Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.2 One SRTS (synchronous residual time stamp) Generating Module. . . . . . . . . . . . . . . . . . . . 87 4.6.1.3 Three Integer Divisor Clock Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.4 Two Precise Clock Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.1.5 Eleven Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.2 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.3 Integer Divisor Clocks (idclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.6.4 Precise Clocks (pclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.6.5 Point Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.6.6 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.6.6.1 SRTS Clock Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.7 SRTS Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6.8 External Memory Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.1 Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3 Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.1 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.2 Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.3 Data Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.4 Control Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.4 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.2 Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.5.3 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.5.4 TDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.5.5 TX_SAR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
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5.5.6 Scheduler Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.5.7 RX_SAR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.5.8 Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.5.9 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.5.10 H.100 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.0 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.1 TDM statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.2 TX SAR statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3 RX SAR statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.4 UTOPIA statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.0 Programming the fast_clk PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 8.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1.1 Precautions During Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.1.2 Precautions During Power Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.1.3 Pull-ups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.2 H.110 Diode Clamp Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 9.0 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.2 UTOPIA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 9.3 External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.4 H.100/H.110 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 9.5 H.100/H.110 Clocking Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.0 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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Figure 1 - Functionl Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ATM Switch Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3 - Transmit Data Flow - TDM to UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4 - Receive Data Flow - UTOPIA to TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - PLL Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6 - TDM Serial to Parallel/Parallel to Serial (SPPS) Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 7 - CAS and MFS Transport on the TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 8 - TDM Data Path Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 9 - TDM Channel Association Structures: TX Channel non-CAS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 10 - TDM Channel Association: RX Channels (Non CAS mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 11 - TDM Channel Association: TX Channels (CAS mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 12 - TDM Channel Association: RX Channels (CAS mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 13 - CAS Change Structure in Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 14 - TX/RX Circular Buffer and Size Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 15 - Silent Pattern Buffer A/B in Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 16 - TDM Circular Buffer (one MultiFrame in T1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 17 - TDM Circular Buffer (one Super Frame in E1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 18 - TDM Circular Buffers (Normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 19 - TDM Circular Buffer (Complete Buffer in E1 mode, Strict Multiframing) . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 20 - TDM Circular Buffer (Complete Buffer in E1 mode, FASTCAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 21 - TDM Circular Buffer (Complete Buffer in T1 mode, Strict Multiframing) . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 22 - TDM Circular Buffer (Complete Buffer in T1 mode, FASTCAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 23 - ATM Cell Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 24 - Transmit Event Scheduler Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 25 - Unsyncrhonised Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 26 - Synchronised Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 27 - Partially Synchronised Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 29 - TX_SAR Control Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 30 - RX_SAR Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 31 - Overrun and Underrun Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 32 - RX_SAR Error Report Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 33 - UTOPIA Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 34 - ATM Mode State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 35 - PHY Mode State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 36 - Cell Format for cells in internal UTOPIA input and output cell FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 37 - Cell Router Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 38 - Match & Mask Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 39 - Short and Long Look-Up Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 40 - VPI/VCI Concatenation and LUT Entry Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 41 - UTOPIA Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 42 - External UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 43 - Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 44 - Integer Clock Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 45 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 46 - Adaptive Cell Reception Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 47 - Rx SRTS Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 48 - Tx SRTS Clock Recovery Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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Figure 49 - Clock Recovery Information Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 50 - mem_clk Output and fast_clk Generation Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 51 - mem_clk Input and mclk Generation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 52 - Non-multiplexed CPU Write Access - Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 53 - Non-multiplexed CPU Read Access - Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 54 - Multiplexed CPU Write Access - Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Figure 55 - Multiplexed CPU Read Access - Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 56 - Non-Multiplexed CPU Interface Write Access - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Figure 57 - Non-multiplexed CPU Interface Read Access - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 58 - Multiplexed CPU Interface Write Access - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 59 - Multiplexed CPU Interface Read Access - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 60 - UTOPIA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 61 - Flowthrough ZBT External Memory Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 62 - Flowthrough ZBT External Memory Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 63 - Flowthrough SSRAM External Memory Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 64 - Flowthrough SSRAM External Memory Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 65 - Late-write External Memory Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 66 - Late-write External Memory Timing - Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 67 - Pipelined ZBT External Memory Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 68 - Pipelined ZBT External Memory Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 69 - Pipelined External Memory Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Figure 70 - Pipelined External Memory Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Figure 71 - H.100 Input, Output, and Frame Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 72 - H.100 Message Channel Clock, Transmission Delay, and Reception Delay. . . . . . . . . . . . . . . . . . . 226 Figure 73 - H.100 Clock Skew (when chip is Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 74 - H.100/H.110 Clocking Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 75 - TDM Bus Timing - Compatibility Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Figure 76 - TDM Data Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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Table 1 - CPU Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2 - Control Memory Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3 - Data Memory Bus Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4 - Data and Control Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5 - H.100/H.110 Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6 - Clock Recovery Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7 - Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8 - UTOPIA Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9 - Phase Lock Loop (PLL) Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10 - Process Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11 - Pin Names Listed by Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12 - Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13 - CPU Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 14 - Control Register (0000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15 - Read/Write Data Register (0004h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 16 - Address High Register (0008h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17 - Address Low Register (000Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 18 - Field Description for the Transmit Event Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 19 - Scheduler Event Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 20 - Maximum number of Events per Frame for Common Transmission Speeds . . . . . . . . . . . . . . . . . . . . 61 Table 21 - Examples of typical Transmit Event Scheduler Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 22 - Description of the Fields for the TX_SAR Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 23 - Description of the Fields for the RX_SAR Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 24 - Payload Sizes for Various Cell Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 25 - RX_SAR errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 26 - Description of the Fields for the RX_SAR Error Report Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 27 - Multiplexer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 28 - Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 29 - idclk_a Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 30 - pclk registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 31 - adapsrts0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 32 - Tx SRTS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 33 - SRTS Pointer Buffer, Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 34 - MT90503 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 35 - Types of Data Memory accesses for each agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 36 - Types of Control Memory Accesses For Each Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 37 - CPU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 38 - CPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 39 - CPU Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 40 - CPU Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 41 - LED1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 42 - LED2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 43 - PLL Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 44 - Intel/Motorola Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 45 - Intel/Motorola Address Rise Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 46 - Intel/Motorla Address Fall Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 47 - Intel/Motorola Data Out Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 48 - Intel/Motorola Data In Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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MT90503 List of Tables
Data Sheet
Table 49 - Intel/Motorola Data Rise/Fall Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 50 - Main Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 51 - Main Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 52 - Main Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 53 - Main Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 54 - Interrupt Flags Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 55 - Interrupt1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 56 - Interrupt2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 57 - Interrupt1 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 58 - Interrupt2 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 59 - Utopia Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 60 - Utopia Clock Generation A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 61 - Utopia Clock Generation B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 62 - Utopia Clock Generation C Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 63 - Control Memory Parity0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 64 - Control Memory Parity1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 65 - Control Memory Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 66 - Data Memory Parity 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 67 - Data Memory Parity 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 68 - Data Memory Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 69 - Utopia Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 70 - Utopia Control1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 71 - Utopia Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 72 - Utopia Status 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 73 - Utopia Interrupt Enable 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 74 - Utopia Counters Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 75 - Cell Loss Counters Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 76 - Port A Look Up Table Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 77 - Port A VPI/VCI Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 78 - Port A Concatenation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 79 - Port A VPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 80 - Port A VCI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 81 - Port A VCI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 82 - Port A VCI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 83 - Port A Cell Arrival Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 84 - Port A Cell Arrival Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 85 - Port A Cell Departure Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 86 - Port A Cell Departure Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 87 - Port A Overflow0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 88 - Port A Overflow1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 89 - Port A Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 90 - Port B Look Up Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 91 - Port B VPI/VCI Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 92 - Port B Concatenation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 93 - Port B VPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 94 - Port B VPI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 95 - Port B VCI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 97 - Port B Cell Arrival Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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MT90503 List of Tables
Data Sheet
Table 98 - Port B Cell Arrival Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 99 - Port B Cell Departure Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 96 - Port B VCI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 100 - Port B Cell Departure Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 101 - Port B Overflow0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 102 - Port B Overflow1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 103 - Port C Look Up Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 104 - Port C VPI/VCI Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 105 - Port C Concatenation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 106 - Port C VPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 107 - Port C VPI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 108 - Port C VCI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 109 - Port C VCI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 110 - Port C Cell Arrival Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 111 - Port C Cell Arrival Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 112 - Port C Cell Departure Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 113 - Port C Cell Departure Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 114 - Port C Overflow0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 115 - Port C Overflow1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 116 - TX_SAR Cell Arrival Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 117 - TX_SAR Cell Arrival Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 118 - RX_SAR Cell Departure Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 119 - RX_SAR Cell Departure Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 120 - TX_SAR Overflow0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 121 - TX_SAR Overflow1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 122 - HEC Byte Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 123 - Unknown Header Routing Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 124 - Unknown OAM Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 125 - GPIO Input0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 126 - GPIO Input1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 127 - GPIO Input2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 128 - TXA Data Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 129 - TXA Data Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 130 - RXA Data Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 131 - RXA Data Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 132 - TXB Data Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 133 - TXB Data Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 134 - RXB Data Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 135 - RXB Data Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 136 - GPIO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 137 - GPIO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 138 - GPIO Output0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 139 - GPIO Output1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 140 - GPIO Output2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 141 - GPIO Output Enable0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 142 - GPIO Output Enable1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 143 - GPIO Output Enable2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 144 - TDM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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Table 145 - TDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 146 - Cut VC TSST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 147 - TSST Underrun Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 148 - TSST CAS Underrun Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 149 - TDM Interrupt 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 150 - TDM Interrupt 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 151 - TDM Interrupt Enable Misc. Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 152 - TDM Write Pointer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 153 - TDM Write Pointer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 154 - TDM Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 155 - TX_SAR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 156 - TX_SAR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 157 - TX_SAR Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 158 - TX_SAR Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 159 - TX_SAR Data Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 160 - TX_SAR Data Write Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 161 - TX_SAR Data Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 162 - TX_SAR Data Cell Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 163 - Percent of Bandwidth Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 164 - Scheduler Test Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 165 - Scheduler Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 166 - Scheduler Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 167 - Frame Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 168 - Scheduler Configuration & Enable 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 169 - Scheduler Configuration & Enable 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 170 - Scheduler Configuration & Enable 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 171 - Scheduler Configuration & Enable 3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 172 - RX_SAR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 173 - RX_SAR Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 174 - RX_SAR Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 175 - RX_SAR Data Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 176 - RX_SAR Data Write Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 177 - RX_SAR Data Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 178 - RX_SAR Data Cell Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 179 - Error Structure Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 180 - Error Structure Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 181 - Error Structure Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 182 - Error Structure Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 183 - Error Structure Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 184 - AAL0 Timeout High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 185 - AAL0 Timeout Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 186 - Error Timeout High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 187 - Error Timeout Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 188 - Treated Pulses Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 189 - Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 190 - Clock Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 191 - Status Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 192 - MCLK Alarm 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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Table 193 - MCLK Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 194 - MCLK Counter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 195 - MCLK Alarm 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 196 - MCLK Alarm 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 197 - TX_SRTS 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 198 - TX_SRTS 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 199 - TX_SRTS 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 200 - TX_SRTS 4 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 201 - TX_SRTS 5 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 202 - Adaptive SRTS0 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 203 - Adaptive SRTS0 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 204 - Adaptive SRTS0 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 205 - Adaptive SRTS0 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 206 - Adaptive SRTS0 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 207 - Adaptive SRTS0 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 208 - Adaptive SRTS0 6 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 209 - Adaptive SRTS0 7 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 210 - Adaptive SRTS0 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 211 - Adaptive SRTS0 9 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 212 - Adaptive SRTS1 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 213 - Adaptive SRTS1 1Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 214 - Adaptive SRTS1 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 215 - Adaptive SRTS1 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 216 - Adaptive SRTS1 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 217 - Adaptive SRTS1 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 218 - Adaptive SRTS1 6 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 219 - Adaptive SRTS1 7 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 220 - Adaptive SRTS1 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 221 - Adaptive SRTS1 9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 222 - Pin Mux 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 223 - Pin Mux 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 224 - Pin Mux 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 225 - Pin Mux 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 226 - Pin Mux 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 227 - Pin Mux 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 228 - Integer Clock Divisor0 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 229 - Integer Clock Divisor0 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 230 - Integer Clock Divisor0 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 231 - Integer Clock Divisor0 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 232 - Integer Clock Divisor0 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 233 - Integer Clock Divisor0 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 234 - Integer Clock Divisor0 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 235 - Integer Clock Divisor0 9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 236 - Integer Clock Divisor0 10 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 237 - Integer Clock Divisor1 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 238 - Integer Clock Divisor1 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 239 - Integer Clock Divisor1 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 240 - Integer Clock Divisor1 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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Data Sheet
Table 241 - Integer Clock Divisor1 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 242 - Integer Clock Divisor1 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 243 - Integer Clock Divisor1 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 244 - Integer Clock Divisor1 9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 245 - Integer Clock Divisor1 10 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 246 - Integer Clock Divisor2 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 247 - Integer Clock Divisor2 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 248 - Integer Clock Divisor2 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 249 - Integer Clock Divisor2 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 250 - Integer Clock Divisor2 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 251 - Integer Clock Divisor2 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 252 - Integer Clock Divisor2 8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 253 - Integer Clock Divisor2 9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 254 - Integer Clock Divisor2 10 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 255 - TX SRTS Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 256 - RX SRTS Debug 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 257 - RX SRTS Debug 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 258 - AAL1 Error Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 259 - Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 260 - Miscellaneous Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 261 - Silent Tone 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 262 - Silent Tone 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 263 - Silent Tone 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 264 - Adaptive Point/SRTS Value 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 265 - Adaptive Point/SRTS Base Address Low 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 266 - Adaptive Point/SRTS Base Address High 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 267 - Adaptive Point/SRTS Write Pointer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 268 - Adaptive Point/SRTS Read Pointer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 269 - Local SRTS Write Pointer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 270 - Local SRTS Read Pointer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 271 - Adaptive Point/SRTS Value 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 272 - Adaptive Point/SRTS Base Address Low 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 273 - Adaptive Point/SRTS Base Address High 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 274 - Adaptive Point/SRTS Write Pointer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 275 - Adaptive Point/SRTS Read Pointer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 276 - Local SRTS Write Pointer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 277 - Local SRTS Read Pointer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 278 - CAS Change Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 279 - CAS Change Buffer Base Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 280 - CAS Change Buffer Base Address High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 281 - CAS Write Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 282 - CAS Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 283 - CAS Timeout High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 284 - CAS Timeout Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 285 - Treated Pulses Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 286 - H.100 Control 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 287 - H.100 Control 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 288 - H.100 Control 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
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Data Sheet
Table 289 - H.100 Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 290 - H.100 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 291 - H.100 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 292 - Register 0128h Frequency Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 293 - Z Divisor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 294 - Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 295 - MCLK - Master Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 296 - Non-multiplexed CPU Interface Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 297 - Multiplexed CPU Interface Intel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 298 - Non-multiplexed CPU Interface Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 299 - Multiplexed CPU Interface Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 300 - t5 Read Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 301 - UTOPIA Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 302 - Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 303 - H.100/H.110 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 304 - H.100/H.110 Clocking Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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MT90503
1.0
1.1
Data Sheet
Introduction
Functional Overview of the MT90503
The MT90503 is an AAL1 SAR, which offers a highly integrated solution for interfacing telecom bus-based systems with ATM networks. The device has the capability of simultaneously processing 2048 bi-directional channels of 64 Kbps. The MT90503 can be connected directly to an H.100 or H.110 compatible bus. The device also offers the capability of using Channel Associated Signalling (CAS) to support Circuit Emulation Service (CES) for Structured Data Transfer (SDT). The interface to the TDM port is provided by a TDM bus, which consists of 32 bi-directional serial TDM data streams at 2.048, 4.096, or 8.192 Mbps, therefore allowing for 2048 bi-directional TDM channels operating at 64 kbps. This TDM bus is compatible with the ECTF H.100 and H.110 specifications. The interface to the ATM domain is provided by three UTOPIA ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Port A is a UTOPIA Level 2 interface which can operate at up to 50 MHz using a 16- or an 8-bit data bus. This port is capable of operating in ATM-mode (single-PHY), in PHY-mode (slave-mode or level 1), or in slave MPHY-mode (Level 2). Port B is a UTOPIA Level 2 interface, which can operate at up to 50 MHz using a 16- or an 8-bit data bus but does not support bus addressing. This port is capable of operating in ATM-mode (single-PHY), in PHY-mode (slave-mode). Port C is a UTOPIA Level 1 interface which can operate at up to 50 MHz using an 8-bit data bus. This port is capable of operating in ATM-mode (master-mode), or in PHY-mode (slave-mode). The MT90503 is capable of performing a UTOPIA loopback from any incoming UTOPIA port to any outgoing UTOPIA port, including a loopback to the port of origin. The loopback capability could be used for dual fibre ring applications. Figure 3 shows the data flow from the H.100/H.110 bus to the TX UTOPIA interface.
Path Controlled by TDM Module Path Controlled by TX SAR Module
H.100/H.110 Bus TDM Bus
Time-Slot Memories
TX SAR Internal Memory
Circular Buffers[15:8] (External Data Memory)
TX UTOPIA Interface
UTOPIA Output
UTOPIA Cell Router
UTOPIA Input FIFO
Path Controlled by UTOPIA Module
Figure 3 - Transmit Data Flow - TDM to UTOPIA
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Figure 4 shows the dataflow from the RX UTOPA interface to the H.100/H.110 bus.
Path Controlled by UTOPIA Module
Data Sheet
RX UTOPIA Interface
UTOPIA Input FIFO
UTOPIA Cell Router
UTOPIA Output FIFO
CPU
CPU Module
External Control Memory
RX SAR non-CBR Portion
H.100/H.110 Bus TDM Bus
Time-Slot Memories
Circular Buffers[7:0] (External Data Memory)
RX SAR CBR Portion
Path Controlled by TDM Module
Path Controlled by RX SAR Module
Figure 4 - Receive Data Flow - UTOPIA to TDM
2.0
2.1
*
Features Detailed Description
UTOPIA Interface
Contains 3 UTOPIA ports with transmit and receive interfaces: Port A: 16-bit or 8-bit UTOPIA Level 2, ATM mode (single-PHY) or PHY mode (single or multi-PHY). Accepts data rates up to 622 Mb/s. Port B: 16-bit or 8-bit UTOPIA Level 2 without bus addressing, ATM mode or PHY mode (restricted to 8-bit when Port A is in multi-PHY mode). Accepts data rates up to 622 Mb/s. Port C: 8-bit UTOPIA, ATM mode or PHY mode
* * * * * * * * * *
Supports cell switching through daisy chained SAR/PHY devices via the UTOPIA interface (AAL5 SARs, AAL1 SARs such as MT90503, and AAL2 SARs such as MT90502). Supports both UNI and NNI header formats Supports any combination of VCI/VPI concatenation up to 16 bits in ATM Receive direction Supports up to 65536 Virtual Circuits Per UTOPIA Port in ATM Receive direction Rapid timing reference cell processing in Receive/Segmentation direction Can eliminate null cells (VPI = 0, VCI = 0) received at UTOPIA A, B, and C port inputs Filters received cells before accessing VCC Look Up Table (LUT) UTOPIA VCC loopback for bi-directional ring functionality (from RX A to TX B and from RX B to TX A) Per-VCC User cell and OAM cell destination control (for VCs that have a LUT entry) Per-UTOPIA-port User cell and OAM cell destination control (for VCs that do not have a LUT entry)
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2.2
* * * * * *
Data Sheet
TDM Interface
H.100/H.110 compatible Low latency TDM bus to TDM bus loopback of up to 2048 channels Programmable value for the null-octet inserted during an underrun situation Receive buffer replay capability or silent pattern insertion for underrun situations Support of CAS and MFS for DS1(ESF) and E1 Automatic Detection of a change in the CAS value, for CAS received in ATM cells, and CAS received from TDM bus
2.3
*
Clock Recovery
SRTS clock recovery: Dual reference VCs (for redundancy) Broadcast SRTS VCs in Transmit /Segmentation direction
*
Adaptive clock recovery Dual reference VCs (for redundancy) Limited jitter, precision enhanced, MCLK (chip clock) to 8 kHz dividers
*
Direct 8 kHz clock recovery: Can generate an 8 kHz reference using one of 8 multipurpose timing reference pins Supports all n * 8 kHz input reference, (1.544 MHz, 2.048 MHz, 19.44 MHz, etc.) up to 12500 * 8 kHz Output high time and low time of the 8 kHz reference output can be modified relative to input signal The eight multipurpose timing reference pins can be used to support many possible clock recovery configurations, including the following reference signals: SEC8K (MVIP), ATM8K (to/from PHY25 or from PHY155), FNXI (SRTS), CT_NETREF (for CT-Bus)
*
Can generate a 20 MHz clock for an external PLL, e.g. MT9042 or MT9044 (output on one of the multipurpose timing reference pins)
2.4
* * *
ATM SAR
Supports AAL1 (with pointer, or without pointer byte), CBR-AAL0, and CBR-AAL5 (AAL5-VTOA) Cell formats Supports partially filled cells, with fills from 4 to 47 bytes AAL1 cell format for "Structured DS1/E1 Nx64 Kbit/s Service" as per ATM Forum AF-VTOA-0078.000 "Circuit Emulation Services Interoperability Specification" (Nx64 Basic Service, DS1 Nx64 Service with CAS, and E1 Nx64 Service with CAS) VCs carrying 1 to 2048 TDM channels TDM to ATM Transmission latency less than 250 s (when minimum voice latency desired, and strict multiframe alignment of voice with CAS not required) TDM to ATM Transmission latency less than 3.25 ms (when strict multiframe alignment of voice with CAS required) ATM to TDM Reception latency less than CDV + 250 s (when minimum voice latency desired, and strict multiframe alignment of voice with CAS not required) ATM to TDM Reception latency less than CDV + 6.250 ms (when strict multiframe alignment of voice with CAS required) Per VCC monitoring (Receive/Reassembly direction):
* * * * * *
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* CDV Monitoring and Delay Correction Fields
Data Sheet
Single cell loss, multiple cell loss, cell misinsertion, AAL1 parity, AAL1-CRC, P-byte Parity, P-Byte Out-of-Range error bits Cell Arrival Counter Underrun Slip Counter Overrun Slip Counter
Per VCC monitoring (Transmit/Segmentation direction): Cell Transmission Counter
* * * * *
Single received cell loss compensated, replacing the payload with a programmable null-octet Support segmentation and reassembly of 2048 full duplex TDM channels (2048 without CAS, subtract one TDM channel for each CAS channel carried) Support of up to 61 ms of CDV in non-multiframing mode, 45 ms in T1 with strict multiframing, 29 ms in E1 with strict multiframing AAL0 Cell Generation / Reception for software implemented SAR function (cell buffer can contain up to 1024 cells) Percentage of bandwidth usage register (Transmit/Segmentation direction)
2.5
* * * * * *
Required External Components
128K/256K/512K x 18 Control Memory (can be used in up to 2 banks) Maximum addressable control memory: 1 MB 128K/256K/512K x 18 Data Memory (can be used in up to 4 banks) Maximum addressable data memory: 4 MB 8 kHz to 16/MHz PLL when H.100/H.110 interface used as master mode Clock driver for mclk_src
2.6
*
Particular Modes of Operation
Test modes TX SAR to RX SAR internal loop-back of some VCs, while MT90503 is running TDM Bus loop-back
2.7
* * * * * * * * *
Miscellaneous
Motorola/Intel CPU Interface (paged memory accesses) Programmable Maximum number of Interrupts per second Multipurpose I/Os LED pin generation for UTOPIA Interface Parity bits on memory and UTOPIA interfaces to ensure clocking and memory access integrity CPU-based OAM cell treatment JTAG (IEEE 1149) Test Access Port MCLK speed of 80 MHz Global reset pin with I/O tri-state
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MT90503
* Global power-down and tri-state
Data Sheet
2.8
* * *
Power
3.3V core and I/O supply All I/Os are 3.3V with 5 V tolerance TDM pins are PCI 5V signalling tolerant (when PCI clamp rail tied to 5 V)
3.0
Pin Designations and Descriptions
The following tables identify each pin of the MT90503 device's main functional areas. A description of each pin is also provided. Notes: 1 2 3 4 5 6 All outputs are +3.3 VDC. All input and output pins that are designated (F) can withstand 5 VDC being applied to them. All input and output pins that are designated (F) are tested with a 50 pF load unless otherwise specified. Designations under the "rst" (reset condition) table column are: X = undefined; Z = high impedance; 1 = high (+3.3 VDC). I/O types include: Output (O), Input (I), Bidirectional (I/O), Power (PWR) and Ground (GND). All buses have pins listed in order from MSB to LSB.
GND pins: A2, A4, A7, A8, A9, A12, A15, A18, A21, A22, A23, A25, A26, A28, B1, B29, D1, D26, D29, E1, E6, E29, G1, G29, H1, H29, J1, J29, L11, L13, L15, L17, L19, M1, M29, N11, N13, N15, N17, N19, R1, R11, R13, R17, R19, R29, T29, U11, U13, U15, U17, U19, V1, W11, W13, W15, W17, W19, AA1, AA29, AB1, AB29, AC1, AD5, AD25, AE1, AE13, AE29, AF1, AF29, AG29, AH1, AH2, AH28, AJ2, AJ4, AJ7, AJ8, AJ9, AJ12, AJ15, AJ18, AJ21, AJ22, AJ23, AJ25, AJ26, AJ28 VDD 3.3V pins: A3, A5, A10, A11, A14, A16, A19, A20, A27, A29, B2, C1, C29, K1, K29, L1, L29, P1, P29, T1, V29, W1, W29, Y1, Y29, AC29, AG1, AH3, AH29, AJ1, AJ3, AJ5, AJ10, AJ11, AJ14, AJ16, AJ19, AJ20, AJ27, AJ29 Pins not connected: A13, B3, B4, B7, B8, B9, B12, B13, B14, B15, B16, C3, C4, C7, C8, C9, C12, C13, C14, C15, D6, D7, D8, D9, D12, D13, D14, D15, D24, E5, E8, E9, E12, E13, E14, E15, E25, M5, M28, T25, W25, AB25, AE4, AE5, AE22, AE23, AE25, AF2, AF23
20
Zarlink Semiconductor Inc.
MT90503
Pin
AE18, AF18, AG18, AH18, AE19, AF19, AG19, AH19, AF20, AG20, AH20, AE21, AF21, AG21, AH21 AE14, AF14, AG14, AH14, AG15, AH15, AE16, AF16 AE12, AF12, AG12, AH12, AF13, AG13, AH13,AJ13 AF11 AE11 AJ17 Z
Data Sheet
Description
Intel/Motorola interface address bus. Can be used as a GPI.
rst
Z
Name
inmo_a [14:0]
I/O
I
Type
TTL (F)
Z
inmo_d [7:0]
I/O
TTL, 4 mA (F)
Intel/Motorola interface data bus, low bits
Z
inmo_d[15:8]
I/O
TTL, 4 mA (F)
Intel/Motorola interface data bus, high bits. Can be used as a GPIO if an 8 bit CPU Interface is used. Master Clock Source. An external clock that is multiplied to generate fast_clk. General Reset Direct Access Select. '1' selects the direct access space. '0' selects the indirection registers contained in the CPU interface. This pin can be connected to a[15] of an address bus but does not behave as an address pin. Intel/Motorola interface chip select Intel/Motorola interface address latch enable Intel write or Motorola read/write Intel read or Motorola data strobe Intel/Motorola interface ready/data acknowledge. This pin is active high for Intel (rdy) and active low for Motorola (ndtack). CPU Interface Mode Select Bit 0. The CPU Interface Mode Select bits must be hardwired. CPU Interface Mode Select Bit 1. CPU Interface Mode Select Bit 2. CPU Interface Mode Select Bit 3. frequency-controllable global interrupt instant global interrupt
mclk_src reset inmo_a_das
I I I
TTL (F) Schmitt (F) TTL, 4 mA (F)
AH17 AG17 AF17 AH16 AG16
Z
inmo_cs inmo_ale inmo_wr_r/w inmo_rd_ds
I I I I O
TTL, 4 mA (F) TTL (F) TTL (F) TTL (F) TTL, 8 mA (F)
Z
inmo_rdy_ndtack
AE20
cpu_mode[0]
I
TTL (F)
AG22 AH22 AF22 AH11 AG11 Z Z
cpu_mode[1] cpu_mode[2] cpu_mode[3] interrupt1 interrupt2
I I I O O
TTL (F) TTL (F) TTL (F) 4 mA (F) 4 mA (F)
Table 1 - CPU Bus Interface Pins
21
Zarlink Semiconductor Inc.
MT90503
Pin AG23, AH23, AE24, AF24, AG24, AH24, AJ24, AF25, AG25, AH25, AG26, AH26, AH27, AA26, AA27, AA28, W27, W28 W26 AG28, AF27, AE26, AE28, AD27, AC26, AC28, AB27, AF28, AE27, AD26, AC25, AC27, AB26, AB28, AA25 Y25 Y27 Y26 Y28 AG27, AF26 rst
X
Data Sheet
Type Description
Control memory address bus
Name
cmem_a [17:0]
I/O
O
4 mA
1 Z
1. cmem_a [18] 2. cmem_cs [1] cmem_d[15:0]
1. O 2. O I/O
4 mA TTL, 4 mA
1. Control memory address bus 2. Control memory chip select 1. Control memory data bus.
1 X X X Z
cmem_cs[0] cmem_bws[0] cmem_bws[1] cmem_r/w cmem_par[1:0]
O O O O I/O
4 mA 4 mA 4 mA 4 mA TTL, 4 mA
Control memory chip select 0 Control memory byte write select 0. Control memory byte write select 1. Control Memory R/W. This signal is only used for late write memories. Control Memory Parity 1:0
Table 2 - Control Memory Bus Interface Pins
22
Zarlink Semiconductor Inc.
MT90503
Pin T28, K26, V28, U29, T27, T26, R28, K25, J27, J26, H28, H27, L25, H25, J28, G27, F25, F27, F29 P25, N28, N26, M27, L28, L26, K28, K27, P28, P26, N29, N27, N25, M26, L27, M25 U25 U26 U27 U28 V27 V26 V25 R27 P27 rst
X
Data Sheet
Description
Data memory address bus
Name
dmem_a[18:0]
I/O
O
Type
4 mA
Z
dmem_d[15:0]
I/O
TTL, 4 mA
Data memory data bus
X X X 1 1 1 1 Z Z
dmem_r/w dmem_bws[0] dmem_bws[1] dmem_cs[0] dmem_cs[1] dmem_cs[2] dmem_cs[3] dmem_par[0] dmem_par[1]
O O O O O O O I/O I/O
4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA TTL, 4 mA TTL, 4 mA
Data Memory R/W. This signal is only used for late write memories. Data memory byte write select 0. Data memory byte write select 1. Data memory chip select 0 Data memory chip select 1 Data memory chip select 2 Data memory chip select 3 Data memory parity 0 Data memory parity 1
Table 3 - Data Memory Bus Interface Pins
Pin AD29 AD28 R26 R25 AF15 AE15
rst
Name
mem_clk_i I
I/O
Type
TTL 4 mA PECL PECL PECL PECL
Description
Data and Control memory clocks Data and Control memory clocks Data and Control memory clocks, PECL Data and Control memory clocks, PECL Data and Control memory clocks, PECL Data and Control memory clocks, PECL
X
mem_clk_o mem_clk_positive_i mem_clk_negative_i
O I I O O
X X
mem_clk_positive_o mem_clk_negative_o
Table 4 - Data and Control Memory Clock Pins
23
Zarlink Semiconductor Inc.
MT90503
Data Sheet
Pin B17, A17, E22, D17, B19, B18, E16, C18, C16, C20, E18, E17, D16, E21, B22, B21, B20, B23, E19, C19, D23, D22, C22, D19, C24, B24, A24, E20, C21, B26, C23, D21 G25 G26 C28 B28 C27 C26 E26 D27 D28 E23 D25 E27 E28 F26 E24
rst
Z
Name
ct_d[31:0]
I/O
I/O
Type
PCI (F)
Description
H.100/H.110 serial data bus
Z Z Z Z Z Z Z Z Z Z Z Z Z
ct_netref1 ct_netref2 ct_c8_a ct_c8_b ct_frame_a ct_frame_b ct_fr_comp ct_c2 ct_c4 ct_c16ct_c16+ ct_sclk ct_sclkx2 ct_mc
I/O I/O I/O I/O I/O I/O O O O O O O O I/O O
Schmitt, 12 mA (F) Schmitt, 12 mA (F) Schmitt, 12 mA (F) Schmitt, 12 mA (F) Schmitt, 12 MA (F) Schmitt, 12 MA (F) 12 mA (F) 12 mA (F) 12 mA (F) 12 mA (F) 12 mA (F) 12 mA (F) 12 mA (F) TTL, 12 mA (F) 4 mA (F)
H.100/H.110 Network Reference 1. H.100/H.110 Network Reference 2. H.100/H.110 8 MHz clock A H.100/H.110 8 MHz clock B H.100/H.110 Frame pulse A H.100/H.110 Frame pulse B H.100/H.110 compatibility frame pulse MVIP 90-bit clock MVIP 90-bit clock times two H-MVIP 16 MHz clock H-MVIP 16 MHz clock SCBUS system clock SCBUS system clock times two H.100/H.110 Message Channel. Open Collector output. H.100/H.110 Message Channel extracted clock. 2 MHz. Nominal duty cycle: 62% high, 38% low. H.100/H.110 Message channel transmit data. When this signal is `0', the MT90503 will drive ct_mc low. When `1', the MT90503 will not drive ct_mc. H.100/H.110 Message channel receive data. The level of this pin directly reflects the value of ct_mc.
X
mc_clock
B27
mc_tx
I
TTL (F)
C25
X
mc_rx
O
4 mA (F)
Table 5 - H.100/H.110 Bus Interface Pins
24
Zarlink Semiconductor Inc.
MT90503
Pin B25 rst Name
ct_vdd5_0 I
Data Sheet
Description
5V power supply used in PCI Buffers of the ct_d[31:0] signals. Can also be connected to 3V power supply. See ct_vdd5_0. See ct_vdd5_0. See ct_vdd5_0.
I/O
Type
D20 D18 C17
ct_vdd5_1 ct_vdd5_2 ct_vdd5_3
I I I
Table 5 - H.100/H.110 Bus Interface Pins (continued)
Pin
E10 D10 C10 B10 E11 D11 C11 B11
rst
Z Z Z Z Z Z Z Z
Name
recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h
I/O
I/O I/O I/O I/O I/O I/O I/O I/O
Type
TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL, 4 mA (F)
Description
Clock recovery general I/O A. This pin can be used as a GPIO. Clock recovery general I/O B. This pin can be used as a GPIO. Clock recovery general I/O C. This pin can be used as a GPIO. Clock recovery general I/O D. This pin can be used as a GPIO. Clock recovery general I/O E. This pin can be used as a GPIO. Clock recovery general I/O F. This pin can be used as a GPIO. Clock recovery general I/O G. This pin can be used as a GPIO. Clock recovery general I/O H. This pin can be used as a GPIO.
Table 6 - Clock Recovery Pins
Pin
Nom Switch (MHz)
0 1 1 1 1 1
rst
Name
I/O
Type
Description
AE17 AH5 AG5 AH4 AG4 AE7
global_tri_state tck tdi X tdo tms trst
I I I O I I
TTL (F) TTL (F) TTL (F) TTL, 4 mA (F) TTL (F) TTL (F)
(PU) Should be 1 for functional mode, 0 for tristate. JTAG Test Clock. Should be 1 when not in use JTAG Test Data In. Should be 1 when not in use JTAG Test Data Out JTAG Test Mode Select. Should be 1 when not in use. JTAG Test Reset. Should be 0 when not in use.
Table 7 - Test Pins
25
Zarlink Semiconductor Inc.
MT90503
Pin
H3 C6 C2 D2 Z
Data Sheet
Description
UTOPIA Port A TX Clock UTOPIA Port A RX Clock PHY alarm A This pin can also act as a GPI. LED signal. When the LED is on, this pin will be '0'. When the LED is off, this pin will be tri-state. This pin can also act as a GPIO. LED signal. When LED is on, this pin will be '0'. When the LED is off, this pin will be tri-state. This pin can also act as a GIPO. 1. UTOPIA Port A TX Cell Available (in ATM) 2. UTOPIA Port A TX Enable (in PHY) 1. UTOPIA Port A TX Enable (in ATM). This pin must be pulled-up externally. 2. UTOPIA Port A TX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port A TX Start of Cell UTOPIA Port A TX Data bus UTOPIA Port A TX Data bus Each of these pins can be used as a GPIO. UTOPIA Port A TX Parity 1. UTOPIA Port A RX Cell Available (in ATM) 2. UTOPIA Port A RX Enable (in PHY) 1. UTOPIA Port A RX Enable (in ATM). This pin must be pulled-up externally. 2. UTOPIA Port A RX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port A RX Start of Cell UTOPIA Port A RX Data bus UTOPIA Port A RX Data bus Each of these pins can be used as a GPI. UTOPIA Port A RX Parity UTOPIA Port B TX Clock UTOPIA Port B RX Clock PHY alarm B This pin can also act as a GPI. LED signal. When LED is on, this pin will be '0'. When the LED is off, this pin will be tri-state. This pin can also act as a GPIO.
rst
Z Z
Name
txa_clk rxa_clk phya_alm phya_rx_led
I/O
I/O I/O I I/O
Type
TTL, 4 mA (F) TTL, 4 mA (F) TTL (F) TTL, 12 mA (F)
H5
Z
phya_tx_led
I/O
TTL, 12 mA (F)
J5 H2 1.Z 2.Z
1. txa_clav 2. txa_enb 1. txa_enb 2. txa_clav
1.I 2.I 1.O 2.O
TTL (F) 4 mA (F)
N2 L5, K2, K3, K4, K5, J2, J3, J4 N4, N5, M2, M3, M4, L2, L3, L4 N3 A6 B6
Z Z Z Z
txa_soc txa_data[7:0] txa_data[15:8] txa_par 1. rxa_clav 2. rxa_enb
O O I/O O 1.I 2.I 1.O 2.O
4 mA (F) 4 mA (F) TTL, 4 mA (F) 4 mA (F) TTL (F) 4 mA (F)
1. Z 2. Z
1. rxa_enb 2. rxa_clav
H4 E2, E3, E4, D3, D4, D5, C5, B5 G3, G4, G5, F1, F2, F3, F4, F5 G2 W4 N1 AB5 W5 Z Z Z
rxa_soc rxa_data[7:0] rxa_data[15:8] rxa_par txb_clk rxb_clk phyb_alm phyb_rx_led
I I I I I/O I/O I I/O
TTL (F) TTL (F) TTL (F) TTL (F) TTL, 4 mA TTL, 4 mA (F) TTL (F) TTL, 12 mA (F)
Table 8 - UTOPIA Interface Pins
26
Zarlink Semiconductor Inc.
MT90503
Pin
T5
Data Sheet
Description
LED signal. When LED is on, this pin will be '0'. When the LED is off, this pin will be tri-state. This pin can also act as a GPIO. 1. UTOPIA Port B TX Cell Available (in ATM) 2. UTOPIA Port B TX Enable (in PHY) 1. UTOPIA Port B TX Enable (in ATM) This pin must be pulled-up externally. 2. UTOPIA Port B TX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port B TX Start of Cell UTOPIA Port B TX Data bus
rst
Z
Name
phyb_tx_led
I/O
I/O
Type
TTL, 12 mA (F)
W2 W3 1Z 2Z
1. txb_clav 2. txb_enb 1. txb_enb 2. txb_clav
1.I 2.I 1.O 2.O
TTL (F) 4 mA (F)
AD2 AA2, AA3, AA4, AA5, Y2, Y3, Y4, Y5 AC3, AC4, AG2, AB2, AB3, AB4 AC2
Z Z
txb_soc txb_data[7:0]
O O
4 mA (F) 4 mA (F)
Z Z
txb_data[13:8] 1. txb_data[14] 2. rxa_addr[4] 1. txb_data [15] 2. txa_addr[4] txb_par 1. rxb_clav 2. rxb_enb
I/O 1.O 2.I 1.O 2.I O 1.I 2.I 1.O 2.O
TTL, 4 mA (F) TTL, 4 mA (F)
UTOPIA Port B TX Data bus Each of these pins can be used as a GPIO. 1. UTOPIA Port B TX Data bus 2. UTOPIA Port A RX Address 4 This pins can be used as a GPIO. 1. UTOPIA Port B TX Data bus 2. UTOPIA Port A TX Address 4 This pin can be used as a GPIO. UTOPIA Port B TX Parity 1. UTOPIA Port B RX Cell Available (in ATM) 2. UTOPIA Port B RX Enable (in PHY) 1. UTOPIA Port B RX Enable (in ATM). This pin must be pulled-up externally. 2. UTOPIA Port B RX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port B RX Start of Cell UTOPIA Port B RX Data bus 1.UTOPIA Port B RX Data bus 2. UTOPIA Port A RX Address bus 1. UTOPIA Port B RX Data bus 2. UTOPIA Port A TX Address bus UTOPIA Port B RX Parity UTOPIA Port C TX Clock UTOPIA Port C RX Clock 1. UTOPIA Port C TX Cell Available (in ATM). 2. UTOPIA Port C TX Enable (in PHY).
AD4
Z
TTL, 4 mA (F)
AD3 P4 P5
Z
4 mA (F) TTL (F) 4 mA (F)
1.Z 2.Z
1. rxb_enb 2. rxb_clav
V2 T3, T4, R2, R3, R4, R5, P2, P3 U3, U4, U5, T2 V4, V5, U1, U2
rxb_soc rxb_data [7:0] 1. rxb_data [11:8] 2. rxa_addr [3:0] 1. rxb_data [15:12] 2. txa_addr [3:0] rxb_par Z Z txc_clk rxc_clk 1. txc_clav 2. txc_enb
I I 1.I 2.I 1.I 2.I I I/O I/O 1.I 2.I
TTL (F) TTL (F) TTL (F) TTL (F)
V3 AG10 AF7 AE10
TTL (F) TTL, 4 mA (F) TTL, 4 mA (F) TTL (F)
Table 8 - UTOPIA Interface Pins (continued)
27
Zarlink Semiconductor Inc.
MT90503
Pin
AF10
Data Sheet
Description
1. UTOPIA Port C TX Enable (in ATM). This pin must be pulled-up externally. 2. UTOPIA Port C TX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port C TX Start of Cell UTOPIA Port C TX Data bus
rst
1. Z 2. Z
Name
1. txc_enb 2. txc_clav
I/O
1.O 2.O
Type
4 mA (F)
AH9 AG9, AF9, AE9, AH8, AG8, AF8, AE8, AH7 AG7 AH6 AJ6
Z Z
txc_soc txc_data[7:0]
O O
4 mA (F) 4 mA (F)
Z
txc_par 1. rxc_clav 2. rxc_enb
O 1.I 2.I 1.O 2.O
4 mA (F) TTL (F) 4 mA (F)
UTOPIA Port C TX Parity 1. UTOPIA Port C RX Cell Available (in ATM) 2. UTOPIA Port C RX Enable (in PHY) 1. UTOPIA Port C RX Enable (in ATM). This pin must be pulled-up externally. 2. UTOPIA Port C RX Cell Available (in PHY). This pin must be pulled-down externally. UTOPIA Port C RX Start of Cell UTOPIA Port C RX Data bus
1. Z 2. Z
1. rxc_enb 2. rxc_clav
AG6 AF6, AE6, AF5, AF4, AE2, AE3, AF3, AD1 AH10
1.Z
rxc_soc rxc_data[7:0]
I I
TTL (F) TTL (F)
rxc_par
I
TTL (F)
UTOPIA Port C RX Parity
Table 8 - UTOPIA Interface Pins (continued)
Pin J25 F28 H26 G28 AC5 AG3
rst
Name pllvss_110 Pllvdd_110 Plllp2_110 pllagn_110 pllvss_300 pllvdd_300
I/O I I I O I I
Type
Description VSS pin for the CT PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections. VDD pin for the CT PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections. Loop-filter pin for the CT PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections. Analog Ground pin for the CT PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections. VSS pin for the FC PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections. VDD pin for the FC PLL. See Figure 5, "PLL Pin Connections," on page 34 for recommended connections.
Table 9 - Phase Lock Loop (PLL) Pins
28
Zarlink Semiconductor Inc.
MT90503
Pin
E7
Data Sheet
Description
rst
Name
proc_out
I/O
O
Type
Process Monitor Pin Output. Must not be connected.
Table 10 - Process Monitor Pins
Pin
A2 A3 A4 A5 A6 GND VDD GND VDD
Location
Pin
B9 B10 B11 B12 B13
Location
N/C recov_d recov_h N/C N/C
Pin
C16 C17 C18 C19 C20
Location
ct_d[23] ct_vdd5_3 ct_d[24] ct_d[12] ct_d[22]
Pin
D23 D24 D25 D26 D27
Location
ct_d[11] N/C ct_c16+ GND ct_c2
1. rxa_clav 2. rxa_enb
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29
GND GND GND VDD VDD GND N/C VDD GND VDD ct_d[30] GND VDD VDD GND GND GND ct_d[5] GND GND VDD GND VDD
B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 C1 C2 C3 C4 C5 C6 C7
N/C N/C N/C ct_d[31] ct_d[26] ct_d[27] ct_d[15] ct_d[16] ct_d[17] ct_d[14] ct_d[6] ct_vdd5_0 ct_d[2] mc_tx ct_c8_b GND VDD phya_alm N/C N/C rxa_data[1] rxa_clk N/C
C21 C22 C23 C24 C25 C26 C27 C28 C29 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
ct_d[3] ct_d[9] ct_d[1] ct_d[7] mc_rx ct_frame_b ct_frame_a ct_c8_a VDD GND phya_rx_led rxa_data[4] rxa_data[3] rxa_data[2] N/C N/C N/C N/C recov_b recov_f N/C N/C N/C
D28 D29 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21
ct_c4 GND GND rxa_data[7] rxa_data[6] rxa_data[5] N/C GND proc_out N/C N/C recov_a recov_e N/C N/C N/C N/C ct_d[25] ct_d[20] ct_d[21] ct_d[13] ct_d[4] ct_d[18]
Table 11 - Pin Names Listed by Location
29
Zarlink Semiconductor Inc.
MT90503
Pin
B1 B2 B3 B4 B5 B6 B7 B8 F1 F2 F3 GND VDD N/C N/C rxa_data[0] 1. rxa_enb 2. rxa_clav N/C N/C rxa_data[12] rxa_data[11] rxa_data[10]
Data Sheet
Location
N/C ct_d[19] ct_d[28] ct_vdd5_2 ct_d[8] ct_vdd5_1 ct_d[0] ct_d[10] VDD GND txa_data[13]
Location
Pin
C8 C9 C10 C11 C12 C13 C14 C15 J3 J4 J5
Location
N/C N/C recov_c recov_g N/C N/C N/C N/C txa_data[1] txa_data[0] 1. txa_clav 2. txa_enb
Pin
D15 D16 D17 D18 D19 D20 D21 D22 L29 M1 M2
Pin
E22 E23 E24 E25 E26 E27 E28 E29 P26 P27 P28
Location
ct_d[29] ct_c16mc_clock N/C ct_fr_comp ct_sclk ct_sclkx2 GND dmem_d[6] dmem_par[1] dmem_d[7]
F4 F5 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G25 G26 G27 G28 G29
rxa_data[9] rxa_data[8] dmem_a[2] ct_mc dmem_a[1] Pllvdd_110 dmem_a[0] GND rxa_par rxa_data[15] rxa_data[14] rxa_data[13] ct_netref1 ct_netref2 dmem_a[3] pllagn_110 GND
J25 J26 J27 J28 J29 K1 K2 K3 K4 K5 K25 K26 K27 K28 K29 L1 L2
pllvss_110 dmem_a[9] dmem_a[10] dmem_a[4] GND VDD txa_data[6] txa_data[5] txa_data[4] txa_data[3] dmem_a[11] dmem_a[17] dmem_d[8] dmem_d[9] VDD VDD txa_data[10]
M3 M4 M5 M25 M26 M27 M28 M29 N1 N2 N3 N4 N5 N11 N13 N15 N17
txa_data[12] txa_data[11] N/C dmem_d[0] dmem_d[2] dmem_d[12] N/C GND rxb_clk txa_soc txa_par txa_data[15] txa_data[14] GND GND GND GND
P29 R1 R2 R3 R4 R5 R11 R13 R17 R19 R25 R26 R27 R28 R29 T1 T2
VDD GND rxb_data[5] rxb_data[4] rxb_data[3] rxb_data[2] GND GND GND GND mem_clk_negative_i mem_clk_positive_i dmem_par[0] dmem_a[12] GND VDD 1. rxb_data[8] 2. rxa_addr[0]
H1 H2
GND 1. txa_enb 2. txa_clav
L3 L4
txa_data[9] txa_data[8]
N19 N25
GND dmem_d[3]
T3 T4
rxb_data[7] rxb_data[6]
H3
txa_clk
L5
txa_data[7]
N26
dmem_d[13]
T5
phyb_tx_led
Table 11 - Pin Names Listed by Location (continued)
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Zarlink Semiconductor Inc.
MT90503
Pin
H4 H5 H25 H26 H27 H28
Data Sheet
Location
dmem_d[4] dmem_d[14] dmem_d[5] VDD rxb_data[1] rxb_data[0]
Location
rxa_soc phya_tx_led dmem_a[5] Plllp2_110 dmem_a[7] dmem_a[8]
Pin
L11 L13 L15 L17 L19 L25
Location
GND GND GND GND GND dmem_a[6]
Pin
N27 N28 N29 P1 P2 P3
Pin
T25 T26 T27 T28 T29 U1 N/C
Location
dmem_a[13] dmem_a[14] dmem_a[18] GND 1. rxb_data[13] 2. txa_addr[1]
H29
GND
L26
dmem_d[10]
P4
1. rxb_clav 2. rxb_enb
U2
1. rxb_data[12] 2. txa_addr[0]
J1
GND
L27
dmem_d[1]
P5
1. rxb_enb 2. rxb_clav
U3
1. rxb_data[11] 2. rxa_addr[3]
J2
txa_data[2]
L28
dmem_d[11]
P25
dmem_d[15]
U4
1. rxb_data[10] 2. rxa_addr[2]
U5
1. rxb_data[9] 2. rxa_addr[1]
W26
1. cmem_a[18] 2. cmem_cs[1]
AB28
cmem_d[1]
AE11
reset
U11 U13 U15
GND GND GND
W27 W28 W29
cmem_a[1] cmem_a[0] VDD
AB29 AC1 AC2
GND GND 1. txb_data[14] 2. rxa_addr[4]
AE12 AE13 AE14
inmo_d[15] GND inmo_d[7]
U17 U19 U25 U26 U27 U28 U29 V1 V2 V3 V4
GND GND dmem_r/w dmem_bws[0] dmem_bws[1] dmem_cs[0] dmem_a[15] GND rxb_soc rxb_par 1. rxb_data[15] 2. txa_addr[3]
Y1 Y2 Y3 Y4 Y5 Y25 Y26 Y27 Y28 Y29 AA1
VDD txb_data[3] txb_data[2] txb_data[1] txb_data[0] cmem_cs[0] cmem_bws[1] cmem_bws[0] cmem_r/w VDD GND
AC3 AC4 AC5 AC25 AC26 AC27 AC28 AC29 AD1 AD2 AD3
txb_data[13] txb_data[12] pllvss_300 cmem_d[4] cmem_d[10] cmem_d[3] cmem_d[9] VDD rxc_data[0] txb_soc txb_par
AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25
mem_clk_negative_o inmo_d[1] global_tri_state inmo_a[14] inmo_a[10] cpu_mode[0] inmo_a[3] N/C N/C cmem_a[15] N/C
V5
1. rxb_data[14] 2. txa_addr[2]
AA2
txb_data[7]
AD4
1. txb_data[15] 2. txa_addr[4]
AE26
cmem_d[13]
V25 V26 V27
dmem_cs[3] dmem_cs[2] dmem_cs[1]
AA3 AA4 AA5
txb_data[6] txb_data[5] txb_data[4]
AD5 AD25 AD26
GND GND cmem_d[5]
AE27 AE28 AE29
cmem_d[6] cmem_d[12] GND
Table 11 - Pin Names Listed by Location (continued)
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Zarlink Semiconductor Inc.
MT90503
Pin
V28 V29 W1 W2
Data Sheet
Location
cmem_d[11] mem_clk_o mem_clk_i GND
Location
dmem_a[16] VDD VDD 1. txb_clav 2. txb_enb
Pin
AA25 AA26 AA27 AA28
Location
cmem_d[0] cmem_a[4] cmem_a[3] cmem_a[2]
Pin
AD27 AD28 AD29 AE1
Pin
AF1 AF2 AF3 AF4 GND N/C
Location
rxc_data[1] rxc_data[4]
W3
1. txb_enb 2. txb_clav
AA29
GND
AE2
rxc_data[3]
AF5
rxc_data[5]
W4 W5 W11 W13 W15
txb_clk phyb_rx_led GND GND GND
AB1 AB2 AB3 AB4 AB5
GND txb_data[10] txb_data[9] txb_data[8] phyb_alm
AE3 AE4 AE5 AE6 AE7
rxc_data[2] N/C N/C rxc_data[6] trst
AF6 AF7 AF8 AF9 AF10
rxc_data[7] rxc_clk txc_data[2] txc_data[6] 1. txc_enb 2. txc_clav
W17 W19 W25 AF14 AF15
GND GND N/C inmo_d[6] mem_clk_positive_o
AB25 AB26 AB27 AG11 AG12
N/C cmem_d[2] cmem_d[8] interrupt2 inmo_d[13]
AE8 AE9 AE10 AH8 AH9
txc_data[1] txc_data[5] 1. txc_clav 2. txc_enb txc_data[4] txc_soc
AF11 AF12 AF13 AJ5 AJ6
mclk_src inmo_d[14] inmo_d[11] VDD 1. rxc_enb 2. rxc_clav
AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG1
inmo_d[0] inmo_wr_r/w inmo_a[13] inmo_a[9] inmo_a[6] inmo_a[2] cpu_mode[3] N/C cmem_a[14] cmem_a[10] cmem_par[0] cmem_d[14] cmem_d[7] GND VDD
AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27
inmo_d[10] inmo_d[5] inmo_d[3] inmo_rdy_ndtack inmo_ale inmo_a[12] inmo_a[8] inmo_a[5] inmo_a[1] cpu_mode[1] cmem_a[17] cmem_a[13] cmem_a[9] cmem_a[7] cmem_par[1]
AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24
rxc_par interrupt1 inmo_d[12] inmo_d[9] inmo_d[4] inmo_d[2] inmo_rd_ds inmo_cs inmo_a[11] inmo_a[7] inmo_a[4] inmo_a[0] cpu_mode[2] cmem_a[16] cmem_a[12]
AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21
GND GND GND VDD VDD GND inmo_d[8] VDD GND VDD inmo_a_das GND VDD VDD GND
Table 11 - Pin Names Listed by Location (continued)
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Pin
AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9
Data Sheet
Location
cmem_a[8] cmem_a[6] cmem_a[5] GND VDD VDD GND VDD
Location
txb_data[11] pllvdd_300 tms tdi rxc_soc txc_par txc_data[3] txc_data[7]
Pin
AG28 AG29 AH1 AH2 AH3 AH4 AH5 AH6
Location
cmem_d[15] GND GND GND VDD tdo tck 1. rxc_clav 2. rxc_enb
Pin
AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3
Pin
AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 GND GND
Location
cmem_a[11] GND GND VDD GND VDD
AG10
txc_clk
AH7
txc_data[0]
AJ4
GND
Table 11 - Pin Names Listed by Location (continued)
Type UTOPIA Port A UTOPIA Port B UTOPIA Port C Clock recovery CPU Bus TDM Bus (H.100/H.110 bus) Control memory Data memory Data and Control Memory Clocks Test PLL Power Ground Miscellaneous No Connects Total:
Input 21 21 12 0 26 1 0 0 3 6 1
Output 12 14 12 0 3 9 23 26 3 0 1
I/O 12 10 2 8 16 39 18 18 0 0 0
Power
Ground
N/C
Total 45 45 26 8 45
4
53 41 44 6 6
2 40
2
6 40
88 1 49 91 104 123 46 90 49
88 1 49 503
Table 12 - Pinout Summary
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Zarlink Semiconductor Inc.
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Data Sheet
pllvdd_0 100pF pllvss_0 0.001uF 10uF
VDD
pllvdd_1 100pF pllvss_1 0.001uF 10uF
VDD
pllp2 301 ohm (1%) pllagn 0.01uF (5%)
Figure 5 - PLL Pin Connections
4.0
4.1
Functional Description1
CPU Interface
The MT90503 CPU module provides an interface permitting programmability from an external microprocessor. The CPU module permits read/write access from MT90503: internal registers, internal and external memories. The CPU interface comprises of: * * * * * Direct Access Select (DAS) as the MSB bit concatenated with a 15-bit address bus 16-bit data bus 2 interrupt signals associated control signals little endian format, unless otherwise specified
The CPU interface can be configured to operate with either Intel or Motorola CPUs. The MT90503 supports both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. If the CPU is operating in 15-bit byte mode addressing with the LSB of its address bus as a byte field, then the inmo_a [14:0] pins of the MT90503 can be connected to the a[15:1] pins of the CPU. If both the MT90503 and the CPU are in 15-bit word mode addressing, then the inmo_a[14:0] pins should be connected to the a[14:0] pins of the CPU. A reduced set of registers `CPU Interface Registers' (0000h to 000Ah) are employed to optimize access time and to permit the CPU to execute indirect read/write accesses via these registers. The CPU also engages these registers to perform direct read/write accesses. The MT90503 and CPU timing relationship is described in section 9.1 on page 211. The CPU Control Register (0100h) provides a software reset capability that allows the CPU to reset the MT90503 except for the CPU interface. The CPU interface can only be reset by a hardware reset.
1. This product incorporates technology licensed from Melita International Corporation.
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4.1.1 CPU Interrupts
Data Sheet
The CPU interface provides a programmable global interrupt capability. The interrupt signal names are `interrupt1' and `interrupt2', pins AH11 and AG11 respectively. Both interrupts have programmability to select their polarity (open collector drive) via registers `interrupt1_conf' and `interrupt2_conf' addresses 0224h and 0226h respectively. Interrupt1 accommodates a capability to program a minimum acceptable period between interrupts. The period is programmed in s units via `interrupt1_conf' register. This provides a `frequency interrupt controller' facility and masks the assertion of further interrupts until the specified period has elapsed. The mask period will commence when the interrupt1_treated[15], register interrupt_flags address 0220h is set. When Interrupt2 is enabled it is always activated when an interrupt condition occurs. Interrupt pins are always tri-stated when inactive. The operation of the CPU interrupt network is common for all modules. When an interrupt is asserted an interrupt flag is set to identify the module where the interrupt was generated. Each module has one or more Interrupt Enable Status Registers where a set interrupt enable bit identifies the source of the interrupt. On completion of the ISR the interrupt must be cleared as the interrupt will remain asserted until it is de-asserted by the user. All Interrupt Enable Status Registers have a symmetrical Status Register. Hence, the bit positioning of the interrupt enables and the associated status bits are identical.
4.1.1.1
Example Interrupt Flow
Upon the initialization of the Global Interrupt pins the following methodology is adopted to identify the source of the interrupt. For this example Interrupt2 is employed and the CPU module will be the source of the interrupt.
4.1.1.2
* * *
Interrupt Initialization
Set interrupt polarity, register interrupt2_conf[15:14]. Enable Interrupt2 for the CPU module, register interrupt2_enable[0] 022Ch. The MT90503 will generate an interrupt on interrupt2 according to the modules enabled in interrupt2_enable. Set the individual CPU interrupt sources by enabling the respective bits in the status0_ie' 0104h register. Within the status0_ie' register there are two possible interrupt sources: internal_read_timeout_ie and inmo_read_done_ie. In the MT90503 Register Description the interrupt bits are labelled IE (Interrupt Enable) in the `Type' column. This register offers the facility to mask/disable unwanted interrupts.
4.1.1.3
Interrupt Servicing
When interrupt2 is asserted (`interrupt2' pin): * * * Read the interrupt flags to ascertain the module raising the interrupt. The CPU module interrupt flag is located in register interrupt_flags[0] 0220h, this bit is named cpureg_interrupt_active. If the cpureg_interrupt_active bit is set, locate the source of the CPU interrupt by reading the `status0' register 0102h, either internal_read_timeout and/or inmo_read_done. The associated status register `status0' 0102h contains internal_read_timeout and inmo_read_done bits. Therefore, to de-assert the interrupt the user must write a 1 to register 0102h bits 3 or 4, internal_read_timeout and inmo_read_done respectively. Only then will the interrupt be de-asserted.
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Zarlink Semiconductor Inc.
MT90503
4.1.2 Intel/Motorola Interface
Data Sheet
The MT90503 CPU interface supports both Intel and Motorola microprocessors, in both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. The MT90503 supports 8 MB of addressable space, therefore indirection addressing is necessary. The microprocessor interface directly addresses five control words, used for indirection accessing. The indirection register contents are shown in tables 13 to 17 inclusively. The timing relationship pertaining to the CPU Interface Registers and Extended Access is defined in section 9.1 on page 211.
0000h
Control Register
0004h
Read/Write Data Register Address High Register Address Low Register
0008h 000Ah
cpu_mode [3:0]
0000 0001 0010 0011
Interface Type
Intel, 16 bit data bus, non-multiplexed Intel, 16 bit data bus, multiplexed Intel, 8 bit data bus, non-multiplexed Intel, 8 bit data bus, multiplexed Motorola, 16 bit data bus, non-multiplexed Motorola, 16 bit data bus, multiplexed Motorola, 8 bit data bus, non-multiplexed Motorola, 8 bit data bus, multiplexed Reserved
address pins
inmo_a[14:0]** (word address) inmo_d[15:1] (word address) inmo_a[14:0] (byte address) inmo_a[14:8]& inmo_d[7:0] (byte address) inmo_a[14:0] (word address) inmo_d[15:1] (word address) inmo_a[14:0] (byte address) inmo_a[14:8]& inmo_d[7:0] (byte address)
data pins
inmo_d[15:0] inmo_d[15:0] inmo_d[7:0] inmo_d[7:0]
direct_access
inmo_a_das inmo_a_das inmo_a_das inmo_a_das
ale
inmo_ale* inmo_ale* inmo_ale* inmo_ale*
0100 0101 0110 0111
inmo_d[15:0] inmo_d[15:0] inmo_d[7:0] inmo_d[7:0]
inmo_a_das inmo_a_das inmo_a_das inmo_a_das
inmo_ale* inmo_ale* inmo_ale* inmo_ale*
1xxx
* The inmo_ale pin is interpreted in all modes. However, it is not necessary in the non-multiplexed modes and can be tied to VCC. **The address placed on the inmo_a[14:0] pins is a word address in 16-bit mode and a byte address in 8-bit mode. The address, when placed on the inmo_d pins, is always a byte address.
Table 13 - CPU Interface Mode Selection
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Zarlink Semiconductor Inc.
MT90503
Field
read_burst_length
Data Sheet
Description
Bit
6:0
Type
RW
Reset
01h
Number of words to prefetch. Setting Words 00h 128 01h 1 02h 2 . . . . . . 7Fh 127 This field is set to 01h for individual (non-sequential) reads. All burst reads greater than 256-bytes must be executed in two or more burst reads. Reset to 0. Set by software when an extended access is initialised. Reset by hardware when the access is completed. Used for extended indirect access only. Extended address bits 3:1. Invalid for extended direct access. Active high write enables. 00 = read access. 01 = write to lower byte. 10 = write to upper byte. 11 = write to entire word. This field is ignored for: extended direct reads and all byte wide extended direct accesses. Read/Write Parity bits.
reserved access_req
7 8
RO PC
0h 0h
extended_a[3:1] write_enable
11:9 13:12
RW RW
0h 0h
extended_parity
15:14
RW
0h
Table 14 - Control Register (0000h)
Field extended_data[15:0]
Bit 15:0
Type RW
Reset 0000h
Description The extended indirect read/write data word register. Invalid for extended direct access.
Table 15 - Read/Write Data Register (0004h)
Field extended_a[32:20] Reserved
Bit 12:0 15:13
Type RW RO
Reset 000h 0h
Description Upper extended address [32:20]. Reset to 000.
Table 16 - Address High Register (0008h)
Field extended_a[19:4]
Bit 15:0
Type RW
Reset 0000h
Description Lower extended address [19:4]. In extended direct addressing, bits 19:16 are employed for 16 bit data bus and bits 19:15 are employed for 8 bit data bus.
Table 17 - Address Low Register (000Ah)
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Zarlink Semiconductor Inc.
MT90503
4.1.2.1 Extended Indirect Accessing
Data Sheet
Extended Indirect Accessing solely employs the registers 0000h to 000Ah to access the 8 MB of addressable memory space. Synopsis: the user writes the access address to registers 0000h, 0008h and 000Ah. Then the MT90503 will read/write to that address and fetch/place the data value from/to register 0004h. For all extended indirect accesses the INMO_A_DAS bit will be held low.
4.1.2.2
Extended Indirect Writes
The following steps must be executed to perform an extended indirect write: 1 2 3 4 5 Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous value holds true. Write the lower address, extended_a[19:4], to register 000Ah. This write may be not be required if previous value holds true. Write the write data, extended_data[15:0], to register 0004h. This write may be not be required if previous value holds true. Write write_enable, extended_parity, access_req=`1' and extended_a [3:1] in a single access to register 0000h. Read the access_req bit located in the Control Register[8] to determine when the write has completed.
The software will set access_req [8] in register 0000h (Step 4 above) and the hardware will reset it when the data write has completed. Therefore, the user can poll this bit to determine when the data write has completed.
4.1.2.3
1 2 3 4 5
Extended Indirect Reads
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous value holds true. Write the lower address, extended_a[19:4], to register 000Ah. This write may be not be required if previous value holds true. Write write_enable = 00, access_req=`1' and extended_a [3:1] in a single access to register 0000h. Wait until access_req is cleared, then read the data from the data field extended_data[15:0], register 0004h. Optional parity check may be ascertained by performing a read on the extended_parity[15:14], register 0000h.
The software will set access_req[8] register 0000h and the hardware will reset it when the data is ready to be read from register 0004h.
4.1.2.4
Extended Direct Accessing
Extended Direct Accessing employs the high and low address registers to perform page addressing. The address within the page is provided directly by the CPU address bus. Similarly the data is fetched/placed directly on the CPU data bus. Synopsis: the user writes the access address to registers 0008h and 000Ah but this performs only the page addressing. Upon assertion of the address within the page the MT90503 will read/write the data with respect to that address. The INMO_A_DAS bit is set when the data read/write occurs. When operating the CPU interface in direct mode with a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 000Ah.
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Zarlink Semiconductor Inc.
MT90503
Data Sheet
However, when operating the CPU interface in direct mode with an 8-bit data bus bits, [19:15] are used for the lower address word.
4.1.2.5
1 2 3 4
Extended Direct Writes
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous value holds true. Write the lower address extended_a[19:16] or [19:15] to register 000Ah. The remaining bits [15:4] or [14:4] are ignored. This write may be not be required if previous value holds true. Write write_enable[13:12] (where applicable) and extended_parity[15:14]. The extended parity write is optional. Write the data value to the address within the corresponding memory page with the INMO_A_DAS bit set.
4.1.2.6
1 2 3 4
Extended Direct Reads
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous value holds true. Write the lower address, extended_a[19:16] or [19:15], to register 000Ah. The remaining bits [15:4] or [14:4] are ignored. This write may be not be required if previous value holds true. Assert the lower address within the memory page and fetch the read data with INMO_A_DAS set. An optional read may be performed to obtain the parity values, extended_parity[15:14] register 0000h.
4.1.3
MT90503 Reset Procedure
The following reset procedure is required to power-up the MT90503. The reset procedure must be adhered at power-up employing the reset pin. Post power-up, the reset procedure can be performed from step 3. 1 2 3 4 Assert the reset pin for at least 1000 MCLK cycles. De-assert the reset pin. All accesses in the remaining reset procedure will employ indirection. Initialise the mem_clk_* bits and write_cache_enable bit via the Control Register bits [13:10], address 0100h. Write the mclk_src frequency at register led1[6:0] and LED Flash Frequency at registers led1[15:7], register address 0120h. Write the LED Flash Frequency units (i.e. ms or s) at register led2[0], address 0122h. Initialise the PLL via register pll_conf, address 0128h. Set bits nreset_* in the Control Register bits [7:0], address 0100h. Initialize the data and control memory types via registers 0240h, 0242h, 0244h, 0248h, 024Ah, and 024Ch Select UTOPIA clocking methodology at register addresses 0230h, 0232h, 0234h and 0236h. Configure the interrupts' active_level for interrupt1 and interrupt2 in register 0224h and 0226h.
5 6 7 8 9
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Zarlink Semiconductor Inc.
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4.2 TDM Module
Data Sheet
The general architecture of the TDM bus consists of three main elements. * * * The TDM bus interface which is coupled directly to the bus pins and manages the timing requirements of the H.100/H.110 interface. The datapath management for transporting the bytes from the TDM bus to the circular buffers (located in the external data memory). The TDM clocking mechanism, this enables the MT90503 to be H.100/H.110 bus master capable and communicates with the clock recovery module.
4.2.1
TDM Bus Interface
The MT90503 TDM Module interfaces with all 32 data streams of the H.100/H.110 bus. The maximum data rate of 8.192 Mbps determines the total bus capacity of 4096 TDM TSST. The MT90503 can process up to: 2048 transmitting TDM TSST and 2048 receiving TDM TSST within one frame of 125s. One less TDM channel is carried for each CAS channel that is desired. If all TDM channels have CAS, then 1024 transmit and 1024 receive channels is the limit. The MT90503 can drive out data on any particular TSST (Time Slot/Stream), or read in data from any particular TSST. Each individual time slot or DS0 on the H.1x0 bus is assigned by a unique TSST number, based on the following equation: timeslot * 32 + stream (timeslot * 2+1) * 32 + stream (timeslot * 4+3) * 32 + stream for 8MHz streams for 4MHz streams for 2MHz streams
TSST =
The timeslot ranges from 0 to 31 for 2MHz streams, from 0 to 63 for 4MHz streams, or from 0 to 127 for 8MHz streams. The 16 lowest data streams are capable of running at a data rate lower than 8.192 MHz. The streams are grouped in fours and each quartet must run at the same data rate. Streams [3:0], [7:4], [11:8] and [15:12] can each run at 2.048, 4.096 or 8.192 MHz as a group. This allows backward compatibility with older, slower TDM buses. In the reduced rate, the data is still latched using the CT_C8_A or _B clock-edge, but using every second or every fourth clock-edge. The streams numbered [31:16] must always run at 8.192 MHz. The TDM bus can also be configured to use only 4, 8, or 16 streams. This configuration requires less processing of TDM bytes and, also allows a reduced mclk speed. The 4-stream mode is useful for conducting tests, while the 16-stream mode allows mclk speed to be cut in half while still allowing half the bandwidth of a full H.100/H.110 bus. When the H.100/H.110 bus is carrying CAS signalling bits, every even stream carries regular TDM data bytes, and is associated with an odd stream that carries CAS bits and the indication of the beginning of the multiframe. For TSSTs that are input to the MT90503, the multiframing is provided by the framer. For TSSTs that are generated by the MT90503, the output multiframing is provided by the MT90503; there is one multiframe which is common to all the T1 channel signals and one multiframe which is common to all the E1 channel signals. On the input, the multiframing is independent for each TSST and the MT90503 synchronises all of them to its multiframe.
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Zarlink Semiconductor Inc.
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TDM Serial to Parallel/Parallel to Serial Module RX TDM TimeSlot Memory 32 x 36 bits
Data Sheet
SPPS0 Four CT_Dx pins per SPPS, all running at the same frequency (2,4,8 MHz) Quad SPPS Converter
SPPS7 Four CT_Dx pins per SPPS, all running at the same frequency (2,4,8 MHz) Quad SPPS Converter
TDM Data Path Controler TX TDM TimeSlot Memory 32 x 32 bits
CT_C8_A CT_C8_B CT_FRAME_A CT_FRAME_B tdm6.cdd
control
address Time-Slot Memory Pointer Synchronizer
Data Transfer Controler
FIG tdm6
Figure 6 - TDM Serial to Parallel/Parallel to Serial (SPPS) Converter Each TSST can be used independently for CAS or regular TDM bytes. For example, if time slot 0 on stream 0 requires signalling bits, then they will be carried on time slot 0, stream 1. However, time slot 1 stream 1 can be used to carry normal TDM data, even if the time slot preceding it is used for signalling. T1 and E1 channel formats can be supported simultaneously. The multiframe bit's polarity and position is programmable and global, and will be accepted at both the input and output. The CAS bits occupy bits [7:4] or [3:0] of the CAS byte, depending on the position within the byte of the multiframe indicator. The only difference between CAS support in E1 or T1 mode is the number of frames in the multiframe. T1 contains 24 frames within its multiframes while E1 contains 16. The CAS bits are latched at the input when the multiframe bit is active, and sent out on the output side during the entire multiframe. When the multiframe bit is at an active polarity, the associated TDM byte is the first byte of the multiframe.
ct_c8 ct_frame ct_d0 ct_d1
A bit 7 A bit 6 A bit 5 A bit 4 A bit 3 A bit 2 A bit 1 A bit 0 A SFS
A's cas[3] A's cas[2] A's cas[1] A's cas[0]
Figure 7 - CAS and MFS Transport on the TDM Bus Figure 7, CAS and MFS Transport on the TDM Bus shows the direct interface of the MT90503 with the TDM bus.
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Data Sheet
The TDM interface is capable of looping back up to 2048 TSSTs with a latency of two TDM frames, or 250 s. This loopback is indicated by the control structures associated to each TSST. The loopback allows any two time-slots and streams to be connected together, and work independently of the speed of each of the streams. The MT90503 can interface with 32 data streams as mentioned in previous paragraphs. Since each TSST can be used to either send or receive data, the MT90503 must tri-state the CT_D pins that are receiving data. To avoid overlap between a sending and a receiving TSST, this must be done before the next one begins.
4.2.2
TDM Bus Clocking Mechanism
The MT90503 can operate as either a primary or secondary H.100/H.110 master clock source. The H.100/H.110 clock (CT_C8) is driven by either CT_C8_A or CT_C8_B. The MT90503 can generate the primary bus clock and all its associated bus clocks (ct_fr_comp, sclk, sclkx2, CT_C16-, CT_C16+, CT_C2 and CT_C4) by using the CT_NETREF signal. The CT_NETREF may be received from another H.100/H.110 bus compatible device or it can be determined by the clock recovery module. In master mode, the MT90503 will generate all the compatibility clocks that are necessary for communicating with MVIP and SCSA TDM interfaces. These include the FR_COMP, C2, C4 and C16 signals for communicating with MVIP buses, and the SCLK and SCLKx2 signals for communicating with Signal Computing System Architecture SCSA buses. The TDM module monitors both CT_C8_A and CT_C8_B signals for clock properties and failure. In every operating mode, both the CT_C8_A and CT_C8_B signals are monitored for clock failure. There are two methods of detecting a clock failure on the bus. Firstly, if the rising edge of the clock does not appear within 35 ns window of the expected period, the clock is flagged as being invalid. Secondly, if a single frame does not contain exactly 1024 clock cycles, then the clock will fail. The MT90503 can be configured to switch to the backup master clock (CT_C8_A or CT_C8_B), upon the detection of a master clock failure. The MT90503 can be programmed as a secondary master and therefore switch to the backup master clock when the external primary master clock source has failed. If the MT90503 switches from a secondary master to master it will re-synchronise the TDM module with the backup clock and generate the compatibility clocks. The MT90503 continually monitors both CT_C8_A and CT_C8_B clocks for a failure condition. The MT90503 can be programmed to automatically switch to its backup clock in case of a failure. The MT90503 is an H.100/H.110 master-capable device and, therefore, is able to generate both CT_C8 clocks and CT_FRAME and compatibility signals. As long as the primary signals on the bus are valid, the MT90503 will synchronise its output to them using a PLL. The MT90503 can also generate the CT_C8 and CT_FRAME signals independently of the PLL, using the local 16 MHz clock. In this case, the output signals have no phase relation with those present on the bus. When the TDM bus interface module has written the received data to the circular buffers, it increments the Time-Slot Memory Pointer that is sent to the TX_SAR.
4.2.3
TDM Datapath
When writing to the external data memory, no return value is expected. However, when reading data, a return value, upon storing the data into an RX TSST, is expected and is required to be written back to the structure memory. The underrun count, which may or may not have been updated, is always written back along with all the other bits of the second word. When the data is received at the time slot memory, it is sent via the TDM datapath to the external data memory. According to which time slot is currently being used, the TDM control structures are read.
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Data Sheet
TDM Data Path Controler Write Back Address (For UR Count) Write Back Data (For UR Count) Detect Underruns (Write Back UR Count Field) TS5 Data Memory Read Access Cache (64 x 48 bits) Read Data Latch Memory 64 x 48 bits
RX TDM Time-Slot Memories
Offset for MFS CPU Write Data
TX Pointer RX Pointer CPU Address
TDM Channel Association Memory (2 x 2048 x 32 bits)
Data Read Process TS7 Data Write Process TS0
Data Memory DMA Controler Data Memory Write Access Cache (256 x 48 bits)
TX TDM Time-Slot Memories
Figure 8 - TDM Data Path Controller When accesses are performed from the TDM channel association memory, the write back to the RX half of the circular buffer is also performed. When this write back is done, the underrun detection bit is written to `0', and a null-octet is inserted in place of the old data byte. The TDM datapath module can be configured to work with 32 H.100/H.110 streams, 16-streams, 8-streams, or 4-streams in order to allow lower clock speeds on the MT90503. The bandwidth requirements for supporting each of the above configurations are described in the Bandwidth section.
4.2.4
TDM Channel Association Structures
TDM channel association structures are located at 0x8000 to 0xBFFE in internal memory. Each structure corresponds to a TDM channel by its TSST order.
4.2.4.1
Non CAS Operation
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 Mode TX/RX Circular Buffer Address and Size RBW 1 0 I
TX/RX Circular Buffer Address and Size: Address and size of the circular buffer in the data memory to which data bytes will be written. I: Initialized Bit. Written by `0' by software, set by hardware when the channel starts being treated. Mode: Channel Mode of operation. "0000"=Normal PCM; others=Reserved. RBW: RX Byte Write. Selects byte that will be written in the low bytes of the data memory word where the TX TDM bytes are written. "00"=Do not write over the low byte; "01"=Write a null byte (usually FFh); "10"=Write silence pattern A; Reserved "11"=Write silence pattern B.
Figure 9 - TDM Channel Association Structures: TX Channel non-CAS mode
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Data Sheet
The control structure in Figure 10, TDM Channel Association: RX Channels (Non CAS mode) on page 44 indicates the mode and options selected for the TDM channel. In the general TX structure, the RBW (RX Byte Write) bits provide the format of the byte that is to be written over the RX byte in the circular buffer. While it is possible to write over the low-byte, there are three possibilities provided if writing over the byte is chosen: writing a null byte or generating one of two silence patterns. The detailed description of the dual-direction buffer is provided in the TDM Circular Buffers section.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 Mode TX/RX Circular Buffer Address and Size C U 1 UR Count OE
TX/RX Circular Buffer Address and Size: Address and size of the circular buffer in the data memory from which data bytes will be readVoice Stream Output Enable. This bit, when set, enables the driving of the Voice Data on the OE: stream. Mode: Channel Mode of operation. "0000"=Normal PCM; Reserved "1000"=Low Latency Loopback others=Reserved. C: Cut VC Status Enable. When `0', the UR Count field is freerunning(256 consecutive underruns will not be considered as a Cut VC). When `1', the UR Count field is used as a consecutive underrun indicator that stops incrementing at 255. U: Underrun Status Enable. When this bit is set and an underrun is detected, the status counters and bits will report this event. UR Count 8 bit underrun count. When the C bit is cleared, acts as a freerunning underrun error counter. : When the C bit is set, it is used as a cut VC detector. In this mode, the counter is cleared each time a valid byte is received. It increments (to a maximum of FFh) each time a byte underrun is detected. When a transition from FEh to FFh occurs, the Cut VC status register, counter and id fields are updated. Must be initialized to FFh by software before enabling VC when C bit is set. Must be initialized to 00h by software before enabling VC when C bit is cleared.
Figure 10 - TDM Channel Association: RX Channels (Non CAS mode) In the receive direction, the control structure retains some of the recurrent features from the transmit structure. The TX circular buffer/size field is the same, which is normal given that the TX and RX circular buffers are common. The information on the address and size is encoded in the same way as in the TX structure. For the reception structure, the high mode bit codes whether the RX channel is transmitting a channel received from ATM or if it is retransmitting information taken from the TDM bus and written into a circular buffer. If the high Mode bit is `0', the channel is ATM; if it is `1', the channel is TDM. By supporting a low latency TDM loopback, the MT90503 conforms to the H.100/H.110 specification. The C and U bits serve as status enable bits. These bits are R/W, and tell the register module whether the register counters and status bits should report errors on this VC. The U bit is the underrun status enable: when this bit is set and an underrun is detected, the TDM register module will increment the global underrun counter and set the underrun detect status bit. The C bit serves at the cut VC detect status enable. When this bit is at `0', the UR count acts as a free running 256-underrun counter. In this case, it serves to compile the total number of underruns that have occurred. When the C bit is at `1', then the UR count serves as a detector for cut VCs. The counter resets to 0 each time a valid TDM byte is received. If an underrun is received, the counter is incremented by one. If the counter ever increments from 254 to 255, then 255 consecutive underruns have been received, indicating there is 32 ms of absent data. This is interpreted as a cut VC and will generate an interrupt. Cell-loss integration periods of greater than 32 ms can be supported by software. Upon UR Count reaching 255, and subsequent interrupt to the CPU, the software can check that the count has not returned to zero (which happens if the cells start to arrive again) at some interval equivalent to the cell-loss integration period.
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4.2.4.2 CAS Operation
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 RX CAS UR 0 0 Mode TX/RX Circular Buffer Address and Size RBW 1 0 FS Offset Last TX CAS I
Data Sheet
TX CAS Force EI CM CASWE
TX/RX Circular Buffer Address and Size: Address and size of the circular buffer in the data memory to which data bytes will be written. I: Initialized Bit. Written by `0' by software, set by hardware when the channel starts being treated. Mode: Channel Mode of operation. "0100"=E1 Strict Multiframing; "0101"=E1 FASTCAS; "0110"=T1 Strict Multiframing; "0111"=T1 FASTCAS; others=Reserved. RBW: RX Byte Write. Selects byte that will be written in the low bytes of the data memory word where the TX TDM bytes are written. "00"=Do not write over the low byte; "01"=Write a null byte (usually FFh); "10"=Write silence pattern A; "11"=Write silence pattern B. : CASWE CAS write enable. "x0"=Leave CAS bits in RX Circular Buffer untouched; "x1"=WriteRX CAS URin RX Circular Buffer in case of underrun; "0x"=Write CAS bits present on the associated odd stream to the TX Circular Buffer; "1x"=WriteTX CAS Forcefield in order to bypass the CAS bits from the associated odd stream. : TX CAS Force TX CAS value that must be written to bypass the CAS bits from the associated odd stream. EI: CAS Enable Ignore. If set, the CAS Enable bit (SFS Bit) will be ignored. Instead, the CAS will be latched at one point for each 16/24 consecutive bytes (for E1 and T1 respectively). : RX CAS UR RX CAS value that will be sent in case of an underrun situation on the RX_SAR side. CM: Cas Monitor. When `1', any change in the TX CAS value will be reported to the CPU. : Last TX CAS Last Value of the TX CAS received from the TDM bus. : FS Offset Frame Offset that must be added in order for internal and external multiframes to coincide. Initialize to "00000" by software. Reserved
Figure 11 - TDM Channel Association: TX Channels (CAS mode) The RX Byte Write bits remain the same to allow the insertion of null patterns as for regular channels. The Mode bits, indicate the possible configurations and combinations of multiframing and CAS insertion: "0100" is E1, "0110" is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of transmitting the data and CAS bytes is being used. FASTCAS is used to lower the latency of Circuit Emulation cells. When using the FASTCAS mode, the multiframe pointer is not used and multiframe integrity is therefore not maintained. In addition, special fields for CAS are added in the two additional words of the structure. The CAS WE (CAS Write Enable) bits are used to determine if the CAS is written back. The TX_CAS field is used so the CPU can insert values of CAS, in place of values from the TDM bus; the RX CAS value is used to compensate for underruns. The Last TX CAS field is used to detect when the CAS value received on the TDM bus has changed. When a CAS value is received, it is written back to the Last TX CAS field in the structure. Whenever a new value arrives, it is compared to the last value. If there is a difference, a CAS change signal is sent to the registers, and the new CAS value is written to the CAS change buffer in the external memory. The Frame Offset field is used to store the offset between the internal and external multiframes in the TX direction. When the TDM bus first obtains an external multiframe, it writes the offset field to the correct value between 0 and
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Data Sheet
23. Subsequently, each time that a byte is written to the circular buffer, the offset field is read, and an offset is established between the internal TDM pointer and the pointer that will be used.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 0 0 Mode TX/RX Circular Buffer Address and Size C U 1 UR Count Man RX CAS ME CM CU CO Last RX CAS OE
TX/RX Circular Buffer Address and Size : Address and size of the circular buffer in the data memory from which data bytes will be readVoice Stream Output Enable. This bit, when set, enables the driving of the Voice Data on the even OE: stream. Mode: Channel Mode of operation. "0100"=E1 Strict Multiframing; "0101"=E1 FASTCAS; "0110"=T1 Strict Multiframing; "0111"=T1 FASTCAS; others=Reserved. C: Cut VC Status Enable. When `0', the UR Count field is freerunning(256 consecutive underruns will be cosidered as a Cut VC). When `1', the UR Count field is used as a consecutive underrun indicator stops th t incrementing at 255. U: Underrun Status Enable. When this bit is set and an underrun is detected, the status counters and bits will report this event CU: CAS Underrun Enable. When this bit is set and an CAS underrun is detected, the status counters and bits will report this : UR Count 8 bit underrun count. When the C bit is cleared, acts as a freerunning underrun error counter. When the C bit is set, it is used as a cut VC detector. In this mode, the counter is cleared each time a valid byte is received. It increments (to a maximum of FFh) each time a byte underrun is detected. When a transition from FEh to FFh occurs, the Cut VC status register, counter and id fields are updated. Must be initialized to FFh by software before enabling VC when C bit is set. Must be initialized to 00h by software before enabling VC when C bit is cleared. CM: CAS Monitor. When `1', any change in RX CAS value will be reported to the CPU. When an underrun occurs, a CAS change will never be reported. CO: CAS Output Enable. This bit, when set, enables the driving of the CAS value out on the associated odd TDM steam. : Last RX CAS This is the value of the last RX CAS sent on the TDM bus. This value is not written if an underrun has occured for this CAS value, ME: Manual CAS Insert. When `1', the Man RX CAS is sent instead of the CAS contained in the t memory. l : Reserved Man RX CAS CAS Value that is sent onto the TDM bus if ME = `1'.
Figure 12 - TDM Channel Association: RX Channels (CAS mode) The channel association structure for multiframe channels is slightly different, with only one bit being positioned differently in the structure. While the circular buffer address and size field is still present and functions in the same way, the mode bits are coded in the same way as they are in the transmit structure for multiframe channels. "0100" is E1, "0110" is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of transmitting the data and CAS bytes are employed. Four new fields are added to allow for CAS management on the RX side with multiframing: * * * * Last RX CAS value that indicates the previous CAS bits received on ATM The CAS monitor bit indicates if a change in the value of CAS is to be reported by the module Man RX CAS is the value of CAS that can be inserted in the place of the one received. This value is only used if the ME bit is set ME bit Manual CAS insert
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Data Sheet
For both TX and RX channels, a change in the value of CAS on a channel where the CAS monitor bit is high will cause the new value to be written to the CAS change buffer in the external memory. This buffer contains all the values that have been detected as different from the previous value, along with the 12-bit time slot and stream value of the TDM channel to which they are associated.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 TSST Number On Which CAS Changed New CAS
FIG tdm26
Figure 13 - CAS Change Structure in Control Memory The Circular Buffer Address/Size field is 15 bits and the addresses are 14 bits each, an indirect method of indicating the size is used. This is done by coding the size by the first `1' that is encountered by reading the field starting from the left. For example, if the lowest bit of the field is `1', the buffer is 128 bytes (mapped on a 256 byte boundary). If the lowest bit was `0' but the second-lowest bit is `1', then the buffer is 256 bytes (mapped on a 512 byte boundary), etc.
b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For 128 word buffers: Address[21:8] 1
0
0
0
0
0
0
0
0
b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Address of Circular Buffer in Data Memory b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For 256 word buffers: Address[21:9] 1 0
0
0
0
0
0
0
0
0
0
b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Address of Circular Buffer in Data Memory
b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For 512 word buffers: Address[21:10] 1 0 0
0
0
0
0
0
0
0
0
0
0
b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Address of Circular Buffer in Data Memory b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For 1024 word buffers: Address[21:11] 1 0 0 0
0
0
0
0
0
0
0
0
0
0
0
b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Address of Circular Buffer in Data Memory
FIG tdm18
Figure 14 - TX/RX Circular Buffer and Size Field
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4.2.5 TDM Circular Buffers
Data Sheet
The TDM module writes the data received from the bus to circular buffers that are assigned on a per-channel basis. The circular buffers' size is variable and is specified in two places, i.e., once in the TDM channel association structure for which each channel has an entry, and once in the TX_SAR or RX_SAR structure which reads or writes to that channel. The TX part of the circular buffer (data read from the TDM bus and written to the circular buffer) is contained in bits 15:8 of each circular buffer word. The RX part of the buffer is contained in the remaining bits, 7:0. This alignment allows for underrun detection and null-pattern insertion in the case of underruns. It also allows the detection of cut VCs. A cut VC is indicated when 256 consecutive underrun bytes are detected. In the non-multiframing mode, the circular buffers are used as a single block. This means that for each channel, up to 1024 bytes of data can be stored in the channel's circular buffer. On the RX side, up to 128 ms of data can be stored for retrieval; therefore, at n = 1 with a packet size of 48 bytes, up to 61 ms of CDV can be compensated. In multiframing mode, each 32-byte division of the circular buffer is used to store the information of one multiframe. In T1 operation, the first 24-bytes of the 32-byte division are used to remember the TDM data from the multiframe. In E1 operation, the first 16-bytes are used for the same purpose. In addition, in byte 31 of each division, the CAS value of the multiframe is stored. In this way, the multiframe portion of the TDM pointer is valid for the TDM data and for the CAS data; only the lowest bits need to be changed to "11111" in order to point to CAS. When write backs are performed, a null byte or one of two silent patterns (background noise) can be inserted in the RX byte. The silent patterns are read from buffers of up to 64 KB. These silent patterns can be used to generate noisy silences.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 Pattern A Byte 0 Pattern A Byte 1 Pattern A Byte 2 Pattern B Byte 0 Pattern B Byte 1 Pattern B Byte 2 The Silent Pattern Buffer is n words long, n ranging from 0 to 65535.
+(n-2)*2 +(n-1)*2
Pattern A Byte (n-2) Pattern A Byte (n-1)
Pattern B Byte (n-2) Pattern B Byte (n-1)
Figure 15 - Silent Pattern Buffer A/B in Control Memory
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High byte +0 +2 +4 +6 +8 +A +C +E +10 +12 +14 +16 +18 +1A +1C +1E +20 +22 +24 +26 +28 +2A +2C +2E +30 +32 +34 +36 +38 +3A +3C +3E TX CAS Reserved RX CAS Low byte RX Byte 0 RX Byte 1 RX Byte 2 RX Byte 3 RX Byte 4 RX Byte 5 RX Byte 6 RX Byte 7 RX Byte 8 RX Byte 9 RX Byte 10 RX Byte 11 RX Byte 12 RX Byte 13 RX Byte 14 RX Byte 15 RX Byte 16 RX Byte 17 RX Byte 18 RX Byte 19 RX Byte 20 RX Byte 21 RX Byte 22 RX Byte 23
Data Sheet
EP b15 b14 b13 b12 b11 b10 b9 b8 OP b7 b6 b5 b4 b3 b2 b1 b0 TX Byte 0 TX Byte 1 TX Byte 2 TX Byte 3 TX Byte 4 TX Byte 5 TX Byte 6 TX Byte 7 TX Byte 8 TX Byte 9 TX Byte 10 TX Byte 11 TX Byte 12 TX Byte 13 TX Byte 14 TX Byte 15 TX Byte 16 TX Byte 17 TX Byte 18 TX Byte 19 TX Byte 20 TX Byte 21 TX Byte 22 TX Byte 23
Underrun Detection Bits
Figure 16 - TDM Circular Buffer (one MultiFrame in T1 mode) The CAS bits are always kept in the highest four bits of the last byte. In addition to storing the data in the circular buffers, the parity bits of the data memory are used to detect underruns generated on the ATM link. When the RX_SAR writes data to the circular buffers, it writes a `1' in the parity bit of the memory's low byte. When the TX_SAR writes data bytes in the buffer, it writes a `0' to the parity bit of the memory's low byte. Therefore, when the TDM reads the data from the circular buffer, it expects to read a `1' from the parity bit.
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Data Sheet
If it reads a `0', this means that an underrun has occurred because not enough cells are being received, or there is too much CDV.
High byte +0 +2 +4 +6 +8 +A +C +E +10 +12 +14 +16 +18 +1A +1C +1E +20 +22 +24 +26 +28 +2A +2C +2E +30 +32 +34 +36 +38 +3A +3C +3E TX CAS Reserved Underrun Detection Bits RX CAS
Low byte RX Byte 0 RX Byte 1 RX Byte 2 RX Byte 3 RX Byte 4 RX Byte 5 RX Byte 6 RX Byte 7 RX Byte 8 RX Byte 9 RX Byte 10 RX Byte 11 RX Byte 12 RX Byte 13 RX Byte 14 RX Byte 15
EP b15 b14 b13 b12 b11 b10 b9 b8 OP b7 b6 b5 b4 b3 b2 b1 b0 TX Byte 0 TX Byte 1 TX Byte 2 TX Byte 3 TX Byte 4 TX Byte 5 TX Byte 6 TX Byte 7 TX Byte 8 TX Byte 9 TX Byte 10 TX Byte 11 TX Byte 12 TX Byte 13 TX Byte 14 TX Byte 15
Figure 17 - TDM Circular Buffer (one Super Frame in E1 mode)
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4.2.6 TDM Circular Buffer Pointers
Data Sheet
The convention that a write pointer points to a byte that is currently being written. In like manner, a read pointer points to a byte that is currently being read. Therefore, a read and write pointer to the same buffer must never cross, or be equal to one another.
4.2.6.1
Non-multiframing mode
The global TDM_write_pointer points to the byte from the TDM bus presently being written to the circular buffers. As in all modes, the TDM_read_pointer is incremented before the TDM_write_pointer, because bytes that come from the TDM bus are written after the frame is completed. Meanwhile, bytes read from the data memory and sent onto the bus are already transmitted by the time the frame is complete. The TDM_write_pnt sent to the TX_SAR is the same as global TDM_write_pointer. The TDM_read_pnt sent to the RX_SAR is one frame ahead of the global TDM_read_pointer. Since the TDM_read_pnt is one more than the global TDM_read_pointer, and the TDM_read_pointer is incremented before the TDM_write_pointer, the TDM_read_pnt will always have a lead of either one or two over the TDM_write_pnt.
High byte Low byte EP b15 b14 b13 b12 b11 b10 b9 b8 OP b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 Valid TDM Bytes Wating to be sent in an ATM Cell tdm _lll_read_pnt +C +E tdm _write_pnt +10 +12 +14 +16 +18 +1A +1C +1E +20 +22 +24 0 0 0 0 0 0 0 0 0 0 0 0 0 TX Byte (Being written by TDM) 0 X X 1 1 1 1 1 1 1 1 0 0 rx_sar_write_pnt Valid TDM Bytes Waiting to be sent on the TDM Bus RX Byte (Being written by TDM) RX Byte (Being written by TDM) tdm _read_pnt RX Byte (Being read by TDM) +6 +8 +A 0 0 0 0 0 0 0 0 0 0 0 0
tx_sar_ read_pnt
+(n-3)*2 +(n-2)*2 +(n-1)*2
0 0 0
0 0 0
Underrun Detection Bits n=Buffer word size {128,256,512,1024}
Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions
Figure 18 - TDM Circular Buffers (Normal mode)
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Data Sheet
Figure 18 TDM Circular Buffers (Normal mode) shows that very few of the positions within the circular buffer are invalid for the SAR pointers.
4.2.6.2
E1/T1 Multiframing (standard)
The TDM pointers change to respect the multiframing standards required by E1 and T1 operation. The pointer has two halves. One half indicates the number of the multiframe that the TDM is writing or reading; the other half is the number of the frame within the multiframe. In the T1 mode, this fraction goes from 0 to 23, while in the E1 mode it ranges from 0 to 15. The same global standards of pointer definition still apply as the pointer still points to an invalid byte. The TDM_write_pnt has a global value, which is the value of the internal multiframe pointer. However, due to the multiframing offset, the TDM_write_pnt can vary by almost an entire frame. Therefore, if the global TDM_write_pointer points to 0.0 (Multiframe 0, frame 0) the individual TDM channels may be written anywhere from 0.0 to 0.23 in the T1 mode, and from 0.0 to 0.15 in the E1 mode. The TDM channels may be written almost an entire frame ahead of the global pointer. The pointer sent to the TX_SAR is the same as the global TDM_write_pointer. The TDM_read_pnt is two multiframes ahead of the TDM_write_pnt. The need for this lead arises from the write backs and from CAS. Since the TDM_write_pnt can be writing up to 15 frames ahead, a lead of at least one multiframe must be given. In addition to this, the CAS must be considered. CAS is written during the multiframe of the tx, which can be up to one multiframe ahead of the global pointer. When CAS is read from the rx side it is read at the beginning of the multiframe. Therefore, to ensure that there is always a difference of at least one in the CAS pointers, the delta between the TDM pointers is established at two multiframes. Furthermore, the read pointer that is sent to the RX_SAR is almost one multiframe ahead. This is necessary because CAS is sent at the end of the multiframe on the ATM side, and is read at the beginning of the multiframe on the TDM side. Therefore, to ensure that the CAS of the multiframe is written by the RX_SAR before the TDM reads it, the pointer passed to the RX_SAR is incremented by one multiframe minus one frame. Therefore, if the TDM_read_pointer would have been 2.5 (two multiframes, five frames), the TDM_read_pnt passed to the RX_SAR is 3.4 (three multiframes, four frames).
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Data Sheet
]
High byte b 15 b14 b13 b12 b11 b10 b9 b8 b7 tx_sar_read_pnt +0 T X MultiFrame 0 b6
Low byte b5 b4 b3 b2 b1 RX MultiFrame 0 b0
tdm_write_pn t (earliest)
+20 TX MultiFrame 1 RX MultiFrame 1
15 byte offset tdm_cas_write_p nt (earliest) tdm_write_pn t (latest) +40 TX MultiFrame 2 RX MultiFrame 2 2 MF offset
tdm_cas_write_p nt (latest) +60 TX MultiFrame 3 RX MultiFrame 3 1 MF offset MINIMUM tdm _cas_read_pnt +80 TX MultiFrame 4 RX MultiFrame 4 rx_sar_write_pnt tdm _read_pnt
+(n*2)-40 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2
+(n*2)-20 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1
n=Buffer word size {128,256,512,1024} Reserved
Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions
Figure 19 - TDM Circular Buffer (Complete Buffer in E1 mode, Strict Multiframing) Figure 19 TDM Circular Buffer (Complete Buffer in E1 mode, Strict Multiframing) shows the TDM circular buffer in the E1 mode. The buffer is only half used for the TDM data. The CAS is located at the end of the buffer, and the write and read pointers are offset by a full three multiframes.
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Data Sheet
High byte b 15 b14 b13 b12 b11 b10 b9 b8 b7 tx_sar_read_pnt +0 T X MultiFrame 0 b6
Low byte b5 b4 b3 b2 b1 RX MultiFrame 0 b0
tdm_write_pn t (earliest)
+20 TX MultiFrame 1 RX MultiFrame 1
15 byte offset tdm_cas_write_p nt (earliest) tdm_write_pn t (latest) +40 TX MultiFrame 2 RX MultiFrame 2 2 MF offset
tdm_cas_write_p nt (latest) +60 TX MultiFrame 3 RX MultiFrame 3 1 byte offset MINIMUM tdm _cas_read_pnt +80 TX MultiFrame 4 RX MultiFrame 4 rx_sar_write_pnt tdm _read_pnt
+(n*2)-40 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2
+(n*2)-20 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1
n=Buffer word size {128,256,512,1024} Reserved
Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions
Figure 20 - TDM Circular Buffer (Complete Buffer in E1 mode, FASTCAS) Figure 20 TDM Circular Buffer (Complete Buffer in E1 mode, FASTCAS) is an E1 circular buffer in the FASTCAS mode. Although the TDM read and write pointers are still significantly offset, the delay has been reduced to nearly zero. This is because the rx_sar_write_pnt and the TDM_read_pnt need only be offset by a single byte, as in non-multiframing mode.
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High byte b 15 b14 b13 b12 b11 b10 b9 b8 b7 tx_sar_read_pnt +0 TX MultiFrame 0 RX MultiFrame 0 b6 Low byte b5 b4 b3 b2 b1 b0
Data Sheet
tdm_write_pnt (earliest)
+20 TX MultiFrame 1 RX MultiFrame 1
23 byte offset tdm_cas_write_p nt (earliest) tdm_write_pnt (latest) +40 2 MF offset TX MultiFrame 2 tdm_cas_write_pnt (latest) +60 TX MultiFrame 3 RX MultiFrame 3 tdm _read_pnt 1 MF offset MINIMUM tdm _cas_read_pnt +80 TX MultiFrame 4 RX MultiFrame 4 rx_sar_write_pnt RX MultiFrame 2
+(n*2)-40 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2
+(n*2)-20 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1
n=Buffer word size {128,256,512,1024} Reserved
Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions
Figure 21 - TDM Circular Buffer (Complete Buffer in T1 mode, Strict Multiframing) Figure 21 TDM Circular Buffer (Complete Buffer in T1 mode, Strict Multiframing) shows a T1 circular buffer in standard multiframing mode. The T1 circular buffer is identical to an E1 circular buffer except that the multiframes are 24 bytes instead of 16 bytes.
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High byte b 15 b14 b13 b12 b11 b10 b9 b8 b7 tx_sar_read_pnt +0 TX MultiFrame 0 RX MultiFrame 0 b6 Low byte b5 b4 b3 b2 b1 b0
Data Sheet
tdm_write_pnt
+20 TX MultiFrame 1 RX MultiFrame 1
tdm_cas_write_pnt +40 2 MF offset TX MultiFrame 2 RX MultiFrame 2
tdm _cas_read_pnt +60 TX MultiFrame 3 RX MultiFrame 3 tdm _read_pnt 1 byte offset MINIMUM
+80 TX MultiFrame 4 RX MultiFrame 4 rx_sar_write_pnt
+(n*2)-40 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2
+(n*2)-20 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1
n=Buffer word size {128,256,512,1024} Reserved
Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions
Figure 22 - TDM Circular Buffer (Complete Buffer in T1 mode, FASTCAS) Figure 22 TDM Circular Buffer (Complete Buffer in T1 mode, FASTCAS) shows a T1 circular buffer in FASTCAS mode. The T1 circular buffer is identical to an E1 circular buffer except for the fact that the multiframes are 24 bytes instead of 16 bytes.
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4.3 4.3.1 TX_SAR Module Overview
Data Sheet
The purpose of the TX_SAR Module is to assemble TDM data bytes into ATM cells to be transmitted to the UTOPIA Module. The TX_SAR Module has no external interfaces, and does not control any of the MT90503's pins. However, it is the connecting block between the TDM module and the UTOPIA Module in the data transmission direction. When the TX_SAR assembles ATM cells, it reads bytes from the circular buffers in data memory and uses these to assemble the ATM cells. In order to transmit CBR ATM cells correctly, a timing algorithm is used to ensure that the ATM cells are assembled and transmitted at the defined data rate. This timing algorithm is implemented using the transmit event scheduler. The transmit event scheduler is a construct in control memory that identifies the time ATM cells need to be transmitted, and the circular buffer from which data for the ATM cell is to be retrieved. ATM cells are capable of carrying a variable number of virtual channels. Therefore, the rate at which cells are transmitted is variable.
4.3.1.1
Support and Trunking for Different Types of ATM Cells
The type of ATM cells the TX_SAR supports includes AAL1, CBR-AAL0, and AAL5-VTOA. The transmit event scheduler is capable of supporting the different data rates which are inherent to the different types of ATM cells. Figure 23 - ATM Cell Formats shows the different formats for the ATM cells that the TX_SAR Module supports. The TX_SAR is also capable of supporting hyperchannels (trunking) of up to 2048 channels per VC. In addition, it can also support AAL0 and AAL5 trunking, providing the number of channels is divisible by the payload bytes.
AAL1 with Pointer Cell 46 Payload Bytes GFC VPI VCI VPI VCI AAL1 without Pointer Cell 47 Payload Bytes GFC VPI VCI VPI VCI AAL0 Cell 48 Payload Bytes GFC VPI VCI VPI VCI AAL5 Cell 40 Payload Bytes GFC VPI VCI VPI VCI
VCI PTI CL HEC CSI SEQ CRC P P P-Byte Payload Byte #0 Payload Byte #1
VCI PTI CL HEC CSI SEQ CRC P Payload Byte #0 Payload Byte #1 Payload Byte #2
VCI PTI CL HEC Payload Byte #0 Payload Byte #1 Payload Byte #2 Payload Byte #3
VCI PTI CL HEC Payload Byte #0 Payload Byte #1 Payload Byte #2 Payload Byte #3
Payload Byte #39 "00000000" "00000000" Length [15:8] Length [7:0] CRC32 [31:24] CRC32 [23:16] CRC32 [15:8] CRC32 [7:0]
Payload Byte #44 Payload Byte #45
Payload Byte #45 Payload Byte #46
Payload Byte #46 Payload Byte #47
Figure 23 - ATM Cell Formats
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4.3.2 4.3.2.1 TX_SAR Event Schedulers Overview
Data Sheet
The purpose of the transmit event scheduler is to ensure that the MT90503 assembles and transmits ATM cells at the appropriate time. This timing function is implemented to reduce data overruns and underruns. Before arriving at the TX_SAR, TDM channel data is written into a variable-length (128 to 1024 bytes) transmit circular buffer, a construct in external data memory, by the TDM Module. Each TDM channel is assigned its own transmit circular buffer (see section 4.2.6 TDM Circular Buffer Pointers). The transmit event schedulers determines when the information will be assembled into ATM cells. The 15 transmit event schedulers are identical, and all have individual configuration registers. Each transmit event scheduler is divided into a programmable number of frames. When configured correctly, each transmit event scheduler frame is constrained to an average of 125 s (i.e. the time required for one byte to be received/transmitted on each TDM channel).
4.3.2.2
The Transmit Event Scheduler Process
Please refer to Figure 24 - Transmit Event Scheduler Process in conjunction with this subsection. The MT90503's 15 transmit event schedulers are all maintained in a designated memory block in the external control memory. Each transmit event scheduler can be programmed to support one of the four types of cells (AAL1 with or without pointer, CBR-AAL0, or AAL5-VTOA). Each of the transmit event schedulers can be enabled or disabled via registers (0610h - 0616h) in order to use less bandwidth if a certain format of ATM cell is not required. Figure 24 - Transmit Event Scheduler Process provides an example of one of the 15 transmit event schedulers in the MT90503. All transmit event schedulers have exactly the same properties, and all perform the same functions. They can be configured individually to handle different VC configurations. Each of the 15 transmit event schedulers is made up of a number of "frames", with each frame containing a number of events. An event, if executed, consists of the assembling and placing in a UTOPIA output FIFO of one ATM cell. The base address, length, and number of events can be programmed for each scheduler frame. Each transmit event scheduler has its own Scheduler Base Address which, in conjunction with an internal frame counter, will locate the events in a specific frame. In order for an ATM cell to be assembled and transmitted at the appropriate time, the following transmit event scheduler process steps are required: 1 2 3 On the reception of a frame pulse, the scheduler scans through the events of the current frame. For each valid event in the current frame, a cell is assembled and transmitted to the UTOPIA module. On the reception of the next frame pulse (125 s later) or upon the completion of the final valid event in the current frame, whichever is later, the scheduler increments current frame, to point to the next frame in the scheduler. The scheduler reads each frame sequentially, returning to frame 0 upon completion of the final frame in the scheduler.
4
An analogy can be made of the above process to a continuous "spinning wheel", where there is a continual selection and reading of events for each transmit event scheduler frame. Table 19 - Scheduler Event Fields provides a description of the fields for one of the transmit event schedulers. Refer to Figure 24 - Transmit Event Scheduler Process to locate the fields.
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Transmit Event Scheduler List
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Fields for the Transmit Event Scheduler Transmit Event Scheduler Format
Fields for the Scheduler Event
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
00000h +0 +2 +4 +6 +2n Reserved +6n Event m Loops when last frame is read Event n-1 (M-2)*2n (M-1)*2n M*2n Frame M-1 Frame M Frame M-2 Frame 3 Event m-1 +4n Frame 2 Frame 1 Event 1 +2 Last Frame (M) +0 Frame 0 Event 0 +0 Scheduler Base Address
Num Env Read 2m Events
Scheduler 0's Info
I
Turn Num
Current Frame
00008h
Scheduler 1's Info
00010h
Scheduler 2's Info
Sched Num
s Tx Structure Address Pointer
00070h
Scheduler 14's Info
MT90503
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Notes: Only 1 of 15 schedulers is shown M = 1 to 2048 frames per scheduler n = 0 to 45 events per frame m = number of events in a frame that are read Frames within a scheduler are executed sequentially with a new frame beginning every 125 s (average). Transmit Event Scheduler List is located at the beginning of Control Memory
Figure 24 - Transmit Event Scheduler Process
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Events never read
Data Sheet
MT90503
4.3.2.3 Transmit Event Scheduler Fields Description
Data Sheet
Table 18 - Field Description for the Transmit Event Scheduler provides a description of the fields for the transmit event scheduler. Please refer to Figure 24 - Transmit Event Scheduler Process to locate the fields. Field I Name of Field Scheduler Initialised Bit Bits Used +0/b15 Description of Field This bit is reset by software immediately before enabling the transmit event scheduler. Hardware will set this bit the first time it reads the scheduler information structure. When the I bit is read at '0' by hardware and the scheduler is used for T1/E1 support, the transmit event scheduler's Current Frame will be written between 0-23 for T1 and 0-15 for E1 in order for frame 0 to correspond to the first byte of a multiframe. Turn Num is a counter used for the implementation of multiframing. The scheduler re-synchronises itself with the multiframe count when Turn Num is 0. Current Frame is used to record the frame position of the transmit event scheduler. Range 0 to (Last Frame) The number of events per frame is 2(Num Env)+1. The same number applies to all frames in the scheduler. Range:000 to 101 (2 to 63 events per frame). All others reserved. Indicates to the scheduler how many events in each frame must be read. The same number applies to all frames in the scheduler. m 0 1 2 . . 31 Scheduler Base Address Pointer to the beginning of the transmit event scheduler Last Frame (M) +4/b14:b0 Events Read 64 2 4 . . 62
Turn Num
Free run counter of scheduler wraps Current Frame
+0/b13:b11
Current Frame
+0/b10:b0
Num Env
Number of events per frame in the scheduler Read 2m First Events
+2/b7:b5
Read 2m Events
+2/b4:b0
This field is appended with "00000" as the LSBs, to form a 20-bit address. Note: A frame must never cross a boundary of its own size in memory. Therefore, if the transmit event scheduler has more than 8 events per frame (32 bytes per frame), then some LSBs of this field must be 0. Last Frame = (number of frames in the scheduler) - 1. If Last Frame = 0, the scheduler is one frame long, if Last Frame = 1, the scheduler is two frames long, etc.
Last Frame (M)
+6/b10:b0
Table 18 - Field Description for the Transmit Event Scheduler
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Data Sheet
The number of events per frame in the scheduler, Num Env, determines how much memory is allocated for each frame in the scheduler: 2 words per event. Within this memory, the scheduler will read only the first 2m events, as stored in the Read 2m Events field. Of the events that are read, only those with the Scheduler Num not equal to `1111' (see Table 19) are executed. No action is taken on events that are read whose Scheduler Num is '1111'.
4.3.2.4
Scheduler Events Fields Description
Table 19 - Scheduler Event Fields provides a description of the fields for the transmit event scheduler entries. Figure 24 - Transmit Event Scheduler Process to locate the fields Field Scheduler Num Name of Field Transmit Event Scheduler Number Start Bit Bits Used +0/b5:b2 Description of Field This field contains the scheduler number. 0000 to 1110 = valid scheduler numbers 1111 = invalid event. No action will be taken on this event The transmit event schedulers are read sequentially. This field indicates the first event that will be carried out when the VC is initialised. Software must set the S bit of only one event once programming of the scheduler is complete. This bit is only relevant until the I bit is set in the TX Control Structure. After the I bit is set, all events with valid scheduler numbers will be executed as they are encountered. This field is the pointer to the TX_SAR Structure used to assemble an ATM cell each time this event is read. This field is appended with "00000" as the LSBs to form a 20-bit address.
S
+0/b0
TX Structure Address Pointer
TX Structure Address Pointer
+2/b14:b0
Table 19 - Scheduler Event Fields
4.3.2.5
Bandwidth Limitations for Transmit Scheduler Events
Transmission Speed 25 Mbps 155 Mbps 622 Mbps Maximum Number of Events per Frame 7 45 183
Table 20 - Maximum number of Events per Frame for Common Transmission Speeds The maximum number of events per frame corresponds to the maximum number of events that can occur in one frame of all the schedulers simultaneously. If the frames are not synchronised (as in Figure 25 - Unsyncrhonised Schedulers), the maximum number of events per frame is the sum of the maximum events in any frame of each scheduler (in this case, 32 events + 21 events = 53 events is the maximum number of events per frame). If the schedulers are synchronised (as in Figure 26 Synchronised Schedulers), the maximum number of events per frame is the worst in any particular frame (in this case, 23 + 17 = 40 events is greater than 6 + 24 = 30 events, so 40 events is the maximum number). If the schedulers are partially synchronised (as in Figure 27 - Partially Synchronised Schedulers), the maximum number of events per frame is the worst in any frame that can possibly align (in this case, 20 + 5 = 25 events is less than 27 + 12 = 39 events which is greater than 20 + 16 = 36 events and 27 + 7 = 34 events so 39 events is the maximum number).
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Data Sheet
Scheduler 0 Frame 0 Frame 1 Frame 2 26 Events 15 Events 32 Events Frame 0 Frame 1
Scheduler 1 21 Events 9 Events
Figure 25 - Unsyncrhonised Schedulers
Scheduler 0 Frame 0 Frame 1 23 Events 6 Events Frame 0 Frame 1
Scheduler 1 17 Events 24 Events
Figure 26 - Synchronised Schedulers
Scheduler 0 Frame 0 Frame 1 20 Events 27 Events Frame 0 Frame 1 Frame 2 Frame 3
Scheduler 1 5 Events 12 Events 16 Events 7 Events
Figure 27 - Partially Synchronised Schedulers
4.3.3
Out of Bandwidth Error
The TX_SAR out-of-bandwidth error indicates that a particular region of the scheduler, or the scheduler as a whole, is overloaded. This error occurs when the TX_SAR lagging by F frames or more, where F is an integer written to register 0608h. The TX_SAR has 125 s to execute all the events in the frame it is servicing at the current time. If all the events in the frame are not executed within 125 s, the TX_SAR continues until the end of the current frame before moving on to events in the next frame. This method reduces the amount of time it has to service the following frame. If the first frame took 150 s to service, then there would only be 100 s left to service the following frame. Therefore, if the second frame is also very full, the TX_SAR would not have the time to finish servicing it and will be late again for the following frame. If frames take an excessively long time to service, the MT90503 may become several frames late. If the MT90503 detects that it is F or more frames late, an out-of-bandwidth error will be declared and the MT90503 will skip the next F frames of events. This action will cause latency in the transmission delay and corrupt data on the VCs until the channel reconverges. The channel reconverges once every 375 frames (47 ms) in "AAL1 with pointer" schedulers, and less often if multiframing is used. The cells that were supposed to be assembled in the F missing frames are skipped, and new cells are assembled with the old data. The out-of-bandwidth error arises from an error
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Data Sheet
with the mapping of the transmit event scheduler. Despite this error, the MT90503 will continue with its operations, however, some cells may be lost.
4.3.3.1
Percent of Bandwidth Register
The TX_SAR incorporates a Percent of Bandwidth register (0510h), which indicates the maximum number of mclk cycles utilised by the TX_SAR process per frame. The Percent of Bandwidth register counts the number of mclk cycles from the time that a frame is received, to the time that all the entries for that frame in the schedulers have been completely handled. This value will be compared to the current maximum value obtained by the TX_SAR process. If the most current value is higher, it is retained and written into the Percent of Bandwidth register. The value in the Percent of Bandwidth register can be cleared by the software. If the TX_SAR takes more than 125 s to assemble the cells of a particular frame, the Percent of Bandwidth register's value will be greater than the number of mclk cycles in the 125 s time frame.
4.3.3.2
Distribution of Events by Software
The events in the transmit event scheduler need to be distributed as evenly as possible. For example, an "AAL1 with pointer" 3-channel VC has three events per 46.875 frames. These events must be spaced out with a distance of 15 or 16 frames between events to prevent irregular data distribution resulting in transmission latency and/or data integrity problems. Consequently, a scheduler 8 * 46.875 = 375 frames in length containing 24 events is required to map the three events per 46.875 frames evenly. The mapping of this information is accomplished by external software. One of the key features of the transmit event schedulers is their programmable length. Since different cells require different sizes of schedulers, the schedulers are capable of handling any scheduler length from 1 to 2048 frames. Refer to Table 21 for examples of transmit event scheduler sizes. ATM Cell Type CBR-AAL0 AAL1 with Pointer AAL1 without Pointer AAL5-VTOA/CBR-AAL0 E1 with CAS T1 with CAS Number of Frames 48 375 47 240 750 1125 Transmit Event Scheduler size in KB (e.g. 32 events per frame) 6* 47 5.875 30 94 141
*Note: 6 KB = 32 events per frame * 48 frames per scheduler * 4 bytes per event
Table 21 - Examples of typical Transmit Event Scheduler Sizes
4.3.4
Mapping of the Transmit Event Scheduler
With the "AAL1 with pointer", the format for the mapping of the transmit event scheduler is asymmetric. The "AAL1 with pointer" format expects a cell every 46.875 frames per channel, a transmit event scheduler with 47 frames that skips the last frame one turn out of eight is required. The MT90503 overcomes this difficulty by creating an extended transmit event scheduler of 375 frames, which is 8 * 46.875. Therefore, the irregularity of the transmit event scheduler is corrected and events can be mapped appropriately. Due to this multiplication, the number of events mapped in the transmit event scheduler for any VC is always a multiple of eight. This means the first event in the transmit event scheduler is always a p-byte event and contains a zero value pointer indicating the start of a structure.
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4.3.5 TX_SAR Control Structures
Data Sheet
TX_SAR control structures are constructs in control memory which contain ATM cell information. When a frame event is read from one of the 15 transmit event schedulers, an ATM cell is assembled. The scheduler event contains the base address that points to the control structure that is used for assembling the ATM cell. The control structure contains all of the fields that are required for assembling the ATM cell. The destination field in the control structure is responsible for telling the UTOPIA Module the destination VC of the assembled ATM cell. For detailed information regarding the destination field, refer to Table 22, 'Description of the Fields for the TX_SAR Control Structure" on page 65. Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure shows a functional block diagram of an example of transmit event scheduler interconnections and pointer flow to the TX_SAR control structure.
Scheduler 0 Scheduler List Frame in Scheduler
00000h 00008h Scheduler 0, Frame 374 00070h Scheduler 0's Info Pointer to current Scheduler 0, Frame 0 Scheduler 0, Frame 1
Scheduler 0, Frame 1
Event 0 Event 1
Event 63
Base address of control structure from Event 1 TX_SAR Control Structure Header of the Structure
TDM Channel 0 Pnt TDM Channel 1 Pnt TDM Channel 2 Pnt
tx_sar_read_pnt
TX/RX Circular Buffer Pointer (Same pointer in Channel Association Memory and in TX_SAR Control Structure)
TDM Channel Association Memory (Internal) TSST 0 TSST 1
Byte read by TX_SAR
tdm_write_pnt
TDM Channel 1's Circular Buffer (in the Data Memory)
TSST 2 TX Side TSST 4093 TSST 4094 TSST 4095 Note: All structures are in the Control memory unless otherwise specified
Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure
RX Side
Byte written by TDM Transmit
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4.3.5.1 TX_SAR Control Structure Fields
Data Sheet
Figure 29 - TX_SAR Control Structure shows the TX_SAR control structure format and data fields held in control memory. Table 22, Description of the Fields for the TX_SAR Control Structure describes the data fields. The header for the ATM cell to be constructed is derived from words +8 and +A in the TX_SAR control structure. The final 8 bits of the cell header, the Header Error Check (HEC), are calculated and inserted by the UTOPIA module. The channel entries, beginning at +16h, are 14-bit pointers to the circular buffers in external data memory, one for each channel in the VC.
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3
+ 0h + 2h + 4h + 6h
b2 b1 b0 BS TXD
First Entry
A Last Entry
SRTS
AAL
CE
Payload Size
Offset
Header Fields
+ 8h + Ah + Ch + Eh + 10h + 12h + 14h
GFC VCI [11:0]
VPI
VCI [15:12] PTI
OAM CLP
P-Byte Counter Current Entry tx_sar_read_pnt Transmitted Cell Counter [31:16] Transmitted Cell Counter [15:0] Channel 0's TX/RX Circular Buffer Pointer Channel 1's TX/RX Circular Buffer Pointer n=number of TDM Channels in the VC Reserved I Seq Hardware Write Back Fields
V + 16h V + 18h V
+(n*2) + 14h
Channel (n-2)'s TX/RX Circular Buffer Pointer Channel (n-1)'s TX/RX Circular Buffer Pointer
+ (n*2) + 16h V
Figure 29 - TX_SAR Control Structure
Field
Name of Field First Entry
Byte Address Offset /Bits Used +0/b15:b12
Description of Field
First Entry
First entry gives the position within the structure of the pointer to the first channel. The field is a word pointer and is constant with a value of 0xB. To allow for future structure updates, its value is programmable. Channel 0's address is located at base_add + (2 * First Entry).
A
Structure Active
+0/b11
This bit indicates whether or not the VC is active. The control structure becomes active when A is set. The A bit is set by software. If the A bit is reset, the control structure will always be ignored. If the A bit is set, hardware may ignore it for other reasons, such as the control structure not being initialised.
Table 22 - Description of the Fields for the TX_SAR Control Structure
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Byte Address Offset /Bits Used +0/b8:b7
Data Sheet
Field
Name of Field Synchronous Residual Time Stamp
Description of Field
SRTS
The SRTS bits indicate the generation of SRTS within the VC. SRTS is either absent, enabled, or enabled and master. Many VCs can be programmed to transmit SRTS, but only one can request a new SRTS value. If many VCs transport SRTS, they must all be of the same size, i.e., the same number of channels, to ensure the validity of the values. If SRTS is generated on the VC, it is packaged within the AAL1 byte of cells 1, 3, 5 and 7 of an 8-cell cycle. The SRTS field should never be enabled on CBR-AAL0 or AAL5-VTOA VCs. If SRTS is enabled on multiple VCs, the events must be mapped in such a way that an event that generated cell # 0 for the master VC occurs before the event that generates cell # 0 for all the other VCs. The SRTS field bits are encoded as follows: 00 = No SRTS 01 = Reserved 10 = Send SRTS 11 = Send SRTS, and request a new SRTS value on Seq = 7 The AAL bits indicate the ATM format to be used to assemble the cells in this structure. The AAL field bits are decoded as follows: 00 = CBR AAL0. Consists of CBR data 01 = AAL5-VTOA. Includes a CRC and a payload size indicator at the end of the cell 10 = AAL1 without pointer. Includes a Sequence number packaged with the cell, as well as the possibility of transmitting SRTS on the VC 11 = AAL1 with pointer. Includes a Sequence number packaged with the cell, and the possibility of transmitting SRTS on the VC
AAL
Adaptation Layer
+0/b6:b5
Table 22 - Description of the Fields for the TX_SAR Control Structure (continued)
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Byte Address Offset /Bits Used +0/b4:b2
Data Sheet
Field
Name of Field Circuit Emulation
Description of Field
CE
The CE field bits indicate the presence of a multiframing standard used within the VC. The multiframing standard changes the way the information is read from the TDM circular buffers, as well as the standard that is used to generate the p-byte. In addition, setting the CE bits to a CAS setting will indicate to the TX_SAR that CAS signaling bits must be inserted at the end of the AAL1 control structure. The field bits are decoded as follows: 000 = No CAS, no multiframe 001 = Reserved 01x = Reserved 100 = T1 without CAS (T1 type circular buffer, but no CAS will be sent in the ATM cells) 101 = T1 with CAS (T1 type circular buffer, with CAS sent in the ATM cells 110 = E1 without CAS (E1 type circular buffer, but no CAS will be sent in ATM cells) 111 = E1 with CAS (E1 type circular buffer, with CAS sent in the ATM cells These bits encode the size of the TDM circular buffer that is to be read from. In T1 and E1 modes, a portion of space in the circular buffer is required to store the CAS values; in the T1 mode 25% is required, and in the E1 mode 50% is required. Half of the TDM circular buffer is used for TX data and half for RX data. The field bits are decoded as follows: 00 = 128 words 01 = 256 words 10 = 512 words 11 = 1024 words Last Entry is the word offset from the 8 kB boundary containing the structure to the last circular buffer pointer in the structure. The TXD field is used to tell the UTOPIA Module the destination of the assembled ATM cell. The TX_SAR Destination field is decoded as follows: 0000 = Discard ATM cell 0XX1 = Send to TXA port 0X1X = Send to TXB port 01XX = Send to TXC port Others = Reserved Broadcasting to multiple ports is allowed.
BS
TX/RX Circular Buffer Size
+0/b1:b0
Last Entry TXD
Last Entry TX_SAR Destination Field
+2/b15:b4 +2/b3:b0
Table 22 - Description of the Fields for the TX_SAR Control Structure (continued)
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Byte Address Offset /Bits Used +4/b15:b10
Data Sheet
Field
Name of Field Payload Size
Description of Field
Payload Size
For fully-filled cells, regardless of type, the payload size field is 30h. For partially-filled cells, the payload size indicates the number of TDM bytes to be placed in each ATM cell. The field range is from 4h to 2Fh. Note: 2Fh is an illegal value for partially-filled AAL1cells For partially-filled AAL5 VTOA, this field must be set to 8h, 10h, 18h, 20h, or 28h. Offset is used when the VC first starts up, and whenever an event with the S bit is set in the transmit event scheduler entry. This shows the delta that must exist between the TX_SAR read pointer and the TDM write pointer within the circular buffer. The value for this offset will change depending on the number of channels in the VC, and on the multiframing standard used. Offset's value is programmed with the maximum number of bytes of a given channel in an ATM cell, plus three. If an error is produced when programming Offset, a global tx_slip will be flagged in the register 0502h, indicating an erroneous configuration and the possibility of corrupted data. The Offset between the tx_wrt_pnt (TDM) and the tx_sar_read_pnt that must be present prior to assembling any ATM cell whose event in the transmit event scheduler has the S bit set. This offset is coded as an integer from normal VCs. It is coded as an multi-frame [1:0] and frame [4:0] number for E1 and T1 VCs. Header information for the cells to be assembled using this TX_SAR control structure. The p-byte counter field is used for the generation of the p-byte within the cell, or within the multiframe structure. The p-byte counter is decremented each time a byte of data is sent, including a CAS byte, but not including an information byte such as the AAL1 byte or the pointer-byte. Whenever the counter reaches 0 and must decrement, its value is reset to p-byte Max field which must be set to 0 by the software. Whenever a p-byte needs to be generated, the seven LSBs of the P-byte Counter are the value of the p-byte, with parity added as the MSB. The decrementing continues until the value of the P-byte Counter reaches 0 and wraps around again, ending the multiframe and beginning a new one.
Offset
Offset
+4/b9:b3
GFC, VPI, VCI, OAM, PTI, CLP P-Byte Counter
Header information P-Byte Counter
+8, +A/b15:b0 +C/b14:b0
Table 22 - Description of the Fields for the TX_SAR Control Structure (continued)
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Byte Address Offset /Bits Used +E/b15:b4
Data Sheet
Field
Name of Field Current Entry
Description of Field
Current Entry
The Current Entry field tells the SAR what the first channel is to be assembled in this cell. The valid values for this field are contained between the First Entry and the Last Entry fields inclusively. The Current Entry field also points to words, and is initialised by software to the word pointed to by the First Entry field. the The Current Entry field is similar the Last Entry field, such that it is defined as the offset between the Current Entry field and the 8 kB boundary in which the structure is contained. The I bit is set by the hardware when a scheduler entry flagged with the Start bit asserted high is encountered, i.e., as soon as the first cell is sent on this VC. This bit is cleared by the software upon initialisation. These bits are reset by software.
I
Structure Initialised Bit
+E/b3
Seq
AAL1 Sequence Number Tx_sar_read _pnt Free running transmitted cell counter
+E/b3:b0
tx_sar_read_ pnt Transmitted Cell Counter
+10/b15:b6 +12, +14/b15:b0
This value is a pointer to the next byte to be read in the TX/RX Circular Buffers. The Transmitted Cell Counter increments each time a cell is transmitted on the VC. The time needed for the counter to wrap-around decreases proportionately with the number of channels in the VC. This field should be reset by software and is used for monitoring. When this bit is high the channel is active. When this bit is '0', the programmable null byte, found in register 0420h, will be transmitted. This field is a pointer to the TX/RX Circular Buffer associated with this channel. "0000 0000" will be appended to this field as the LSBs to form a 22-bit address in data memory.
V
TDM Channel Valid Channel N's TX/RX Circular Buffer Pointer
+16 to end/b15 +16 to end/b13:b0
Channel N's TX/RX Circular Buffer Pointer
Table 22 - Description of the Fields for the TX_SAR Control Structure (continued)
4.3.6 4.3.6.1
Miscellaneous TX_SAR Features T1 with CAS and E1 with CAS Cell Format Mapping
For the transmission of T1 with CAS and E1 with CAS, the number of frames required is 9000 and 6000 respectively. But, because the number of frames mapped in a full size transmit event scheduler is always a multiple of eight, the MT90503 handles large size schedulers by dividing the size by eight, and mapping eight times less events (1125 for T1 with CAS and 750 for E1 with CAS). This results in a latency of one frame.
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4.3.6.2 Support of Partially-Filled Cells
Data Sheet
The MT90503 is capable of supporting partially-filled cells, as long as the number of channels in the VC is smaller or equal to the cell fill. A single transmit event scheduler can be created to accommodate several sizes of AAL1, CBR-AAL0 or AAL5-VTOA ATM cells. AAL1 with pointer ATM cells can be used by this format, since the number of data bytes per ATM cell is always constant. For example, the 240-entry transmit event scheduler is capable of accommodating partially-filled cells of 4-, 5-, 6-, 8-, 10-, 12-, 15-, 16-, 20-, 24-, 30-, or 40-bytes per cell.
4.3.6.3
TX_SAR FIFO
The TX_SAR transmits cells contained in its data cell FIFO when there are no events to be processed. The TX SAR's data FIFO can be used to store AAL0 cells as well as OAM cells, therefore, CPU-based OAM cell generation is supported.
4.4
RX_SAR Module
The RX_SAR module performs processing on ATM cells received from the UTOPIA module. Cells placed in the RX_SAR input FIFO by the UTOPIA module are read, processed, and then written into the appropriate multi-cell circular buffer in external control memory. The processing involves identifying the VC corresponding to the cell, examining the cell for errors, determining where to place the data, and monitoring the status of circular buffers. The RX_SAR module also directs data cells to the data cell FIFO from which the CPU can read them. The RX_SAR module does not connect to any external pins, interfacing instead with the UTOPIA module, CPU interface, and external memory controller. Global pointers are shared between the RX_SAR and TDM modules. ATM cells that are received by the MT90503 are processed by the UTOPIA module and can be directed to any of three TX output FIFOs or to the 32-cell RX_SAR input FIFO. Those cells that are forwarded to the RX_SAR are directed to the SAR portion (cells to be formatted into TDM streams), to the data cell portion (to be examined by the CPU), or to both. For cells directed to the SAR portion, the RX_SAR uses control information in the RX_SAR Control Structures (Section 4.4.2) to extract the payload data from the received cell and store it into TDM channel RX Circular Buffers located in external data memory.
4.4.1
Treatment of Data Cells
Data cells, such as those containing OAM information, are placed in a programmable length FIFO in external control memory. The length of the FIFO is stored in register 070Eh. The CPU can read a data cell at any time, after obtaining the address of the FIFO (register 070Ch) and the read pointer (register 0708h). The CPU can be alerted to the presence of data cells via an interrupt that triggers if either of two events occur: the interrupt can be generated when the FIFO becomes more than half full or the interrupt can be generated if a data cell has been present in the FIFO for longer than a programmable period of time (registers 0720h, 0722h). This interrupt can be enabled through register 0220h. When ready to process the information, the CPU obtains a read pointer to the information from register 0708h and reads the information through 26 word accesses. Cells with the OAM bit set in the PTI portion of the header can be directed to the data cell FIFO on a per VC basis. The same is true for non-OAM cells. In addition, unknown non-OAM cells, and/or unknown OAM cells can also be sent to the data cell FIFO (all unknown non-OAM cells are directed to the same location(s)).
4.4.2
Control Structure
For each VC directed to the SAR portion of the RX_SAR, an RX_SAR control structure exists in external control memory. The structure, similar to that of the TX_SAR, contains information on how to process a cell including: * what type of traffic is being carried (AAL1, CBR-AAL0, AAL5-VTOA)
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* * * * * * * the size of the circular buffers for the data how to act in the case of an overrun or underrun the multiframing standard in place expected presence of CAS enabled errors, the size of the payloads information necessary to detect and correct for errors a pointer to each circular buffer, one for each channel in the VC
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 +A +C +E +10 +12 +14 +16 +18 rx_sar_write_pnt Monitored Min Lead Monitored Max Lead Slip Free rx_sar_write_pnt Received Cell Counter [31:16] Received Cell Counter [15:0] PBI First Entry Last Entry Max Used Bytes in RX Circular Buffer P -byte counter Current Entry I Last Seq 2nd Last Seq AAL BS IM CE FC
Data Sheet
SE LE AE PE Payload Size
V V
Channel 0's TX/RX Circular Buffer Pointer Channel 1's TX/RX Circular Buffer Pointer
+(n*2)+14
V
Channel (n-2)'s TX/RX Circular Buffer Pointer Channel (n-1)'s TX/RX Circular Buffer Pointer
+(n*2)+16 V
Reserved
n = number of TDM channels in the VC
Figure 30 - RX_SAR Control Structure
Field First Entry
Name of Field First Entry
Byte Address Offset/Bits Used +0/b15:b12
Description of Field First entry field gives the position within the structure of the pointer to the first channel. The field is a word pointer and is constant with a value of 0xB. To allow for future structure updates, its value is programmable. Channel 0's address is located at base_add + (2 * First Entry).
Table 23 - Description of the Fields for the RX_SAR Structure
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Field AAL Name of Field Adaptation Layer Byte Address Offset/Bits Used +0/b8:b7 Description of Field
Data Sheet
The AAL bits indicates the ATM format used to assemble the cells in this structure. The AAL bits are decoded as follows: 00 = CBR AAL0 01 = AAL5-VTOA 10 = AAL1 without pointer 11 = AAL1 with pointer These bits encode the size of the entire TX/RX circular buffer that is to be written into. In T1 and E1 modes, a certain portion of the space in the buffer is required to store the CAS values; in the T1 mode 25% is required and in the E1 mode 50% is required. The eight MSBs of each word in the TX/RX Circular buffer are used for TX data and the remaining 8 bits for RX data. These bits are decoded as follows: 00 = 128 words 01 = 256 words 10 = 512 words 11 = 1024 words Initialisation method for rx_sar_write_pnt '0' = initialise rx_sar_write_pnt to nearest boundary: either tdm_read_pnt + (Max used bytes in TX/RX Circular buffer) 1 OR tdm_read_pnt + 1 '1' = initialise rx_sar_write_pnt to (Max used bytes in TX/RX Circular buffer)/2 This initialisation method will be used when the first cell is received and each time a slip (an overrun or underrun) occurs. The circuit emulation bits indicate the multiframing standard used within the VC. These bits are decoded as follows: 000 = No CAS, no multiframe 001 = Reserved 01x = Reserved 100 = T1 without CAS 101 = T1 with CAS 110 = E1 without CAS 111 = E1 with CAS FASTCAS is enabled when FC is asserted high. If FASTCAS is used, then the receive pointer used for regular TDM bytes and for CAS bytes is not the same. CAS is written one multiframe before TDM bytes in FASTCAS. When FC is deasserted, regular multiframing is employed: CAS is written in the same multiframe as TDM bytes. Last Entry is the word offset from the 8 kB boundary containing the structure to the last circular buffer pointer in the structure. When set, overrun and underrun slips will generate an RX_SAR Error Report Structure (Figure 32) in the error FIFO in control memory.
BS
TX/RX Circular Buffer Size
+0/b6:b5
IM
Initialisation Method
+0/b4
CE
Circuit Emulation
+0/b3:b1
FC
FASTCAS Enable
+0/b0
Last Entry
Last Entry
+2/b15:b4
SE
Slip Error Report Enable
+2/b3
Table 23 - Description of the Fields for the RX_SAR Structure (continued)
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Field LE Name of Field Cell Loss and Insertion Error Report Enable AAL1 Byte Report Enable P-Byte Error Report Enable Byte Address Offset/Bits Used +2/b2 Description of Field
Data Sheet
When set, single cell losses, multiple cell losses and cell misinsertions will generate an RX_SAR Error Report Structure (Figure 32) in the error FIFO in control memory. When set, AAL1 CRC-3 and CRC-3/Seq Num parity errors will generate an RX_SAR Error Report Structure (Figure 32) in the error FIFO in control memory. When set, p-byte parity errors, p-byte absent and p-byte framing errors will generate an RX_SAR Error Report Structure (Figure 32) in the error FIFO in external control memory. This field indicates the range of valid positions in bytes of the rx_sar_write_pnt relative to the tdm_rx_read_pnt before a cell is received. In no case can this value be 0.
AE
+2/b1
PE
+2/b0
Max Used Bytes in RX Circular Buffer Payload Size
Max Used Bytes in RX Circular Buffer
+4/b15:b6
Payload Size
+4/b5:b0
For fully-filled cells, regardless of type, the payload size field is 30h. For partially-filled cells, the payload size indicates the number of TDM bytes in each ATM cell. The field range is from 4h to 2Fh. Note: 2Fh is an illegal value for partially-filled AAL1cells For partially-filled AAL5 VTOA, this field must be set to 8h, 10h, 18h, 20h, or 28h. Initialized to '0' by software. This field is a counter used to detect p-byte framing errors. When a p-byte is detected, this counter is loaded with the p-byte's value. Each time a TDM byte is received, the counter is decremented. When the counter reaches the Current Entry it should be reset to the First Entry and the rx_sar_write_pnt should point to the beginning of the multiframe if applicable. When it decrements below 0, the counter resets to its maximum. Any time a p-byte is received, its value should match the value in this field, or a p-byte framing error will be detected. Current Entry indicates which TDM channel the RX_SAR is currently writing to the circular buffers. The current entry is defined as being the offset from the 8 KB boundary containing the structure and the "TX/RX Circular Buffer Pointer" being read from the structure. Current Entry is initialised to the value of First Entry, increments up to Last Entry, and then wraps around to First Entry. This field should be initialised by software to 0Bh. Note: This field should not be written to while the VC is active.
PBI P-Byte Counter
P-Byte Initialization P-Byte Counter
+6/b15 +6/b14:b0
Current Entry
Current Entry
+8/b11:b0
Table 23 - Description of the Fields for the RX_SAR Structure (continued)
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Field rx_sar_wr ite_pnt Name of Field RX_SAR write pointer Byte Address Offset/Bits Used +A/b15:b4 Description of Field
Data Sheet
This is a pointer to the location where the next byte will be written in each TX/RX Circular Buffer. It is common to all TX/RX Circular buffers controlled by the RX_SAR Control Structure. In the E1/T1 mode, this field is divided in multiframe [6:0] and frame[4:0]. Only the lower part of the field is used to point to the TX/RX Circular Buffer.
I
Structure Initialised Bit Last Seq 2nd Last Seq
+A/b3
This bit must be reset by software before enabling the VC in the LUT. The bit is set by hardware after receiving the first cell. Last received AAL1 sequence number. Second-last received AAL1 sequence number. The Slip-free rx_sar_write_pnt is the same as the rx_sar_write_pnt except that slips (overruns and underruns) do not affect its value. A 32-bit free running cell counter used for monitoring activity on a VC and for statistical purposes. This field can be initialised to '0' by software.
Last Seq Last Seq Slip Free rx_sar_wr ite_pnt Received Cell Counter V Channel N's TX/RX Circular Buffer Pointer 2nd
+A/b2:b0 +C/b2:b0 +10/b15:b4
Slip-free RX_SAR write pointer Received Cell Counter
+12/b15:b0 +14/b15:b0
TDM Channel Valid Channel N's TX/RX Circular Buffer Pointer
+16 to end/b15 +16 to end/b13:b0
When this bit is high the channel is active. When this bit is reset, all received bytes on the channel are discarded. This field is a pointer to the TX/RX Circular Buffer associated with this channel. "0000 0000" will be appended to this field as the LSBs to form a 22-bit address in external data memory.
Table 23 - Description of the Fields for the RX_SAR Structure (continued) Memory containing the control structures is divided into 8 KB blocks. Zero or more control structures can exist in a block. Control structures must be fully contained in a single block. The pointers Current Entry and Last Entry are relative to the 8 KB block boundary in which their structure resides. The Buffer Size (BS) field indicates the size of the Receive Circular Buffers. Though the Buffer Size is indicated in words, the received data occupies only the lower byte of each word; the data to be transmitted occupies the upper bytes. Selection of size: 128, 256, 512, or 1024 words, depends on the amount of available memory and on the CDV for the VC. The receive half of the buffer must be capable of holding twice the maximum CDV (peak CDV) plus the packetisation size of the cells in the VC plus two additional bytes. Additional space must be added if E1 or T1 formats are employed (the buffer must be twice as big for E1 and a 4/3 of the size for T1). To convert the maximum CDV from ms into bytes, a data rate of 8000 bytes/s must be applied. The packetisation size is defined as the maximum number of bytes a channel can contain in a single cell of the VC. To find the maximum CDV supported by the buffer, the value of the "Max Used Bytes In Circular Buffer" field must be divided by two and multiplied by 125 s/byte. Because a larger buffer will cause more delay through the RX_SAR, the choice of the value of "Max Used Bytes In Circular Buffer" must be made as a compromise between the CDV supported and the delay inserted by the RX_SAR. In the T1/E1 multiframe mode, the value of "Max Used Bytes In Circular Buffer" must be an integer number of frames and is counted in a multiframe/frame fashion. The
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Data Sheet
five MSBs select a number of multiframes and the five LSBs a number of frames. In strict muliframing, the five LSBs are always set to '00000'; they can be any value in FASTCAS. Setting the multiframing standard in the circuit emulation (CE) field will change the way the information is read from the TDM circular buffers, as well as the standard that is used to interpret the p-byte. In addition, setting the CE bits to a CAS setting will indicate to the RX_ SAR that CAS signalling bits should be expected at the end of the AAL1 structure. The payload size represents the number of TDM bytes in the cell and does not include pointer or AAL1-bytes.
Format AAL1 with pointer, non-p-type cell AAL1 with pointer, p-type cell CBR-AAL0
TDM Bytes 16 16 16
Bytes Transmitted 17 18 16
Payload Size 16 16 16
Table 24 - Payload Sizes for Various Cell Formats
4.4.3
Errors
Error CRC error CRC/Sequence Number Parity error Coverage AAL1 cells AAL1 cells AAL1 cells AAL1 cells AAL1 cells AAL1 cells AAL1 cells AAL1 cells AAL1 cells all cells all cells See Figure 31. See Figure 31. CSI = 1, CRC = 010, Seq. num = 110, parity bit = 1. Even parity not observed: a parity error has occurred. Sequence numbers 1, 2, 4 received. Cell 3 has been lost Sequence numbers 1, 2, 4, 3 received. A cell misinsertion has occurred Sequence numbers 1, 2, 5 received. Cells 3, 4 have been lost. P-byte = 0100110, parity bit = 0. Even parity not observed: a p-byte parity error has occurred P-byte received = 0x52, Structure length for that VC = 0x18. P-byte is too large P-byte is 0x15 when 0x17 was expected. Example
Category AAL1 Byte
Cell loss/misinsertion
Single cell loss cell misinsertion Multiple cell loss
P-byte errors
P-byte parity error P-byte out-of-range P-byte framing error P-byte absent
Slip errors
Overrun Underrun
Table 25 - RX_SAR errors Within the four categories of errors, there are eleven possible errors. All but slip errors (overruns and underruns) pertain only to AAL1 cells. For the following errors, the only action taken is the generation of an error report structure (Section 4.4.4): * * * * CRC errors CRC/sequence number parity errors multiple cell loss p-byte parity
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* * * out-of-range framing absent errors
Data Sheet
It is the responsibility of the CPU and associated software to act upon notification that an error has occurred. The exceptions to this policy are * * * * single cell loss (a dummy cell is inserted and treated before accepting the received cell; the received cell counter is incremented by only one) cell misinsertion (the misinserted cell is discarded and the received cell counter is not incremented) overruns (data is lost and read/write pointers are adjusted) underruns (bytes are inserted according to information set in registers 0420h and read/write pointers are adjusted).
.
TDM read pointer RX_SAR
INVALID BYTE VALID BYTE VALID BYTE VALID BYTE
TDM read pointer Max used bytes in RX Circ. Buff. RX_SAR
INVALID BYTE VALID BYTE Max used bytes in RX Circ. Buff. VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE
INVALID BYTE INVALID BYTE INVALID BYTE RX_SAR INVALID BYTE Write Pointer INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE Underrun TDM read pointer Max used bytes in RX Circ. Buff.
Write pointer INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE Normal
Write pointer INVALID BYTE Overrun
Note: For a description of Max Used Bytes in Circular Buffer see Table 23 (+4/b15:b6). Figure 31 - Overrun and Underrun Examples
4.4.4
Error Report Structure
Four categories of errors can be enabled in the RX_SAR structure: * * * * slip errors cell loss & misinsertion errors AAL1 byte errors p-byte errors
For each cell containing an error for which the error category is enabled, an 8-byte error report structure is generated and stored in a FIFO in external control memory. From here, the CPU can read the FIFO and treat the errors.
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Data Sheet
As per the Data Cell FIFO, the CPU can read the error FIFO at any time after obtaining the address to the FIFO (registers 0714h, 0716h) and the read pointer to the RX_SAR Error Report Structure (register 0710h). Again, an interrupt can be generated that will trigger if either of two events occurs: when the FIFO becomes more than half full or if an error report structure has been present in the FIFO for longer than a programmable period of time (register 0724h, 0726h). This interrupt can be enabled in register 0220h. Errors of more than one type on the same cell will result in one error report structure being created indicating all types of errors on that cell. The exception to this is cell misinsertion. Since the cell is discarded once the misinsertion has been detected, no further errors can be found on the misinserted cell.
b15 b14 b13 b12 b11 b10 b9 +0 +2 +4 +6 b8 b7 b6 b5 b4 b3 b2 b1 b0
PA RX_SAR Structure Base Address[19:5] PF PR PP AC AP OR UR M ML SL Last Seq Received Cell Counter [31:16] Received Cell Counter [15:0]
Seq
Figure 32 - RX_SAR Error Report Structure
Field RX_SAR Structure Base Address [19:5] Seq Last Seq
Name of Field RX_SAR Structure Base Address [19:5] Sequence Number Last Sequence Number Received Cell Counter P-Byte Absent Error P-Byte Framing Error P-Byte Range Error
Byte Address Offset/bits Used +0/b14:b0
Description of Field Base address of the RX_SAR Control Structure that caused the Error Report Structure to be generated. Appended with "00000" as the LSBs to form a 20-bit address. Sequence number of the cell that caused the Error Report Structure to be generated. Sequence number of the cell which preceded the one that caused the Error Report Structure to be generated. Cell number of the cell that caused the Error Report Structure to be generated. A p-byte was expected but was not detected in the cell that caused the error. The p-byte that was detected did not match the p-byte that was expected. The p-byte that was detected was out-of-range; the 7-bit p-byte must not be 94-126 and must be less than the sequence length of the corresponding VC. 127 signifies a dummy offset value. The p-byte detected did not match its parity bit. There was an error detected in the CRC-3. The AAL1 byte detected did not match its parity bit.
+2/b2:b0 +2/b5:b3
Received Cell Counter PA PF PR
+4/b15:b0 +6/b15:b0 +0/b15 +2/b15 +2/b14
PP AC AP
P-Byte Parity Error AAL1 Byte CRC-3 Error AAL1 Byte Parity Error
+2/b13 +2/b12 +2/b11
Table 26 - Description of the Fields for the RX_SAR Error Report Structure
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OR UR M Overrun Slip Underrun Slip Cell Misinsertion +2/b10 +2/b9 +2/b8
Data Sheet
The circular buffer associated with a channel receiving data from the cell was overrun. The circular buffer associated with a channel receiving data from the cell was underrun. The sequence number of the cell indicated that a cell was misinserted. This error is always preceded by a single cell loss. The sequence number of the cell indicated that multiple cells were lost. The sequence number of the cell indicated that a single cell was lost.
ML SL
Multiple Cell Loss Single Cell Loss
+2/b7 +2/b6
Table 26 - Description of the Fields for the RX_SAR Error Report Structure (continued)
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4.5 4.5.1 UTOPIA Module Overview
Data Sheet
The purpose of the UTOPIA module is to provide an external interface with the ATM domain. The MT90503 complies with The ATM Forum's specifications: af-phy-0017.000 and af-phy-0039.000. The MT90503 uses octet-level handshaking on its UTOPIA interface. The UTOPIA module is responsible for accepting cells from four input interfaces, examining the cells and, based on the source and information in the header, sending the cell to one or more of the four output interfaces. The UTOPIA module also calculates and appends the HEC to outgoing ATM cells.
Control Memory Interface Cell Router RXA UTOPIA Interface (external) RXB UTOPIA Interface (external) RXC UTOPIA Interface (external) TX_SAR Interface (internal) Cell FIFO (4 cells) Match & Mask Cell FIFO (4 cells) Known cells LUT Append RX Structure Pointer Unknown cells Cell FIFO (32 cells) Cell FIFO (32 cells) TXA UTOPIA Interface (external) TXB UTOPIA Interface (external) TXC UTOPIA Interface (external) RX_SAR Interface (internal)
Cell FIFO (4 cells)
Cell FIFO (32 cells)
Cell FIFO (4 cells)
Cell FIFO (32 cells)
AAL1 Byte rxa_clk domain txa_clk domain
AB
Discard
SRTS and Adaptive Clock Recovery Interface rxb_clk domain txb_clk domain
rxc_clk domain
txc_clk domain
mclk domain
Figure 33 - UTOPIA Module The UTOPIA interface consists of three ports, labelled A, B, and C. Port A is a Level-2 ATM (single PHY), single PHY or multi-PHY port and can operate at 50 MHz. Port B is a Level-2 ATM (single PHY) or single PHY port and can operate at 50 MHz. It is restricted to an 8-bit data bus when port A is in multi-PHY mode. Port C is a Level-1 ATM or PHY port. In addition to ports A, B, and C, the UTOPIA accepts cells from the TX_SAR and routes cells to the RX_SAR and to the data cell FIFO in external control memory.
4.5.2
UTOPIA Interfaces
Each of the three ports is divided into two portions: a receive portion and a transmit portion. The TX_SAR and the receive portions are each connected to a 4-cell FIFO. These FIFOs are read on a round-robin basis by the Cell Router (See "Cell Router" on page 82.). The RX_SAR and the transmit portions are each connected to a 32-cell FIFO. The ports are configurable with the following options: * Port A's transmit portion can be ATM, PHY, with a 16-bit or 8-bit data bus.
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* * * * * * Port A's receive portion can be ATM or PHY, with a 16-bit or 8-bit data bus. Port A can be Level-2 multi-PHY. Port B's transmit portion can be ATM or PHY, with a 16-bit or 8-bit data bus.* Port B's receive portion can be ATM or PHY, with a 16-bit or 8-bit data bus.* Port C's transmit portion can be ATM or PHY, with an 8-bit data bus. Port C's receive portion can be ATM or PHY, with an 8-bit data bus.
Data Sheet
*When Port A is in Level-2 multi-PHY mode, Port B must have an 8-bit data bus.
Each receive interface can be independently enabled or disabled. If disabled, the receive interface will stop accepting cells after the current cell has been received. When the transmit portions of a port are in PHY mode, the SOC, data bus, and parity output pins can be tristated when the port is not selected. This allows the MT90503 to share a data bus, SOC, and parity lines with other devices (i.e. independent ENB signals and CLAV signals for each PHY device, controlled by a single ATM device). In the case of a receive PHY, the generation of the rx_clav signal is independent of the state machine. The rx_clav signal is asserted high at any time when a complete cell can be received. Thus as soon as the first byte of a cell is received, and there is no room for another cell in the input FIFO, the rx_clav signal will be asserted low. In the case of a Level-2 PHY, the rx_clav's will only be driven when the address was placed on the bus during the previous cycle.
4.5.3
Errors on received cells
If the MT90503 receives a short cell on any one of its three ports, the cell will be discarded, and a new cell will be started when the second SOC signal is set. If the SOC is not set after the 53rd byte of a received cell, subsequent bytes are ignored until a a new SOC is received. Data received on all of the three ports is examined for parity errors and an interrupt is raised if an error is found. Cells are not discarded if a parity error is detected. Register 0304h indicates on which port the parity error is detected. The ATM HEC is not examined on received cells.
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Zarlink Semiconductor Inc.
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4.5.4 Transmit and Receive State Machines for ATM and PHY Modes
Data Sheet
Idle
Cell not available OR tx_clav=0
No room for 1 cell
Idle (rx_enb=1)
No room for 1 cell
Room for 1 cell
Cell available AND tx_clav=1
Tx 1st Byte (tx_soc=1, tx_enb=0)
tx_clav=1
Room for at least 1 cell tx_clav=0
Idle (rx_enb=0)
rx_clav=0 OR rx_soc=0
rx_clav=1 AND rx_soc=1
53 bytes sent
Tx Next Byte (tx_soc=0, tx_enb=0)
<53 Bytes AND tx_clav=0
Discard Cell Idle
tx_clav=0 rx_clav=1 AND rx_soc=1
Rx 1st Byte
rx_clav=0
tx_clav=1
rx_clav=1 <53 Bytes AND rx_clav=0 53 bytes received
<53 Bytes AND tx_clav=1
Rx Next Byte
rx_clav=1
Idle
rx_clav=0
Transmit State Machine <53 Bytes AND rx_clav=1
Receive State Machine
Figure 34 - ATM Mode State Machines
No room for 1 cell
Idle (rx_clav=1)
No room for 1 cell
Idle
Room for 1 cell Cell available AND tx_enb=0*
Cell not available OR tx_enb=1**
Room for at least 1 cell
Idle (rx_clav=0)
rx_enb=1** OR rx_soc=0
rx_enb=0* AND rx_soc=1
Tx 1st Byte (tx_soc=1, tx_clav=1)
tx_enb=0*
tx_enb=1**
Discard Cell
Rx 1st Byte
rx_enb=1**
53 bytes sent
rx_enb=0* AND rx_soc=1
rx_enb=0* <53 Bytes AND rx_enb=1** 53 bytes received
Tx Next Byte (tx_soc=0, tx_clav=1)
<53 Bytes AND tx_enb=1**
Idle
tx_enb=0*
tx_enb=1**
Rx Next Byte
rx_enb=0*
Idle
rx_enb=1**
<53 Bytes AND tx_enb=0* Receive State Machine
<53 Bytes AND rx_enb=0* Transmit State Machine
NOTE: PHY Mode Transmit and Receive refers to the direction of cells as per the UTOPIA specification.
* If MPHY L2, add "AND rx_addr matches" ** If MPHY L2, add "OR rx_addr doesn't match"
Figure 35 - PHY Mode State Machines
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4.5.5 Cell Router
Data Sheet
Cells are read on a round-robin basis from the four input FIFOs. Cells from the TX_SAR that contain a '0' in the MSB of the TXD field (see Figure 36 on page 82) are written into the output FIFOs designated by the three LSBs of the TXD field. Cells from the TX_SAR that contain a '1' in the MSB of the TXD field and cells from the RXA, RXB, and RXC ports are handled based on the VPI/VCI of the cell. The TXD field for a cell is the same as the TXD field in the TX_SAR control structure that created the cell (see Figure 29 on page 65). Cells written into the RX_SAR output FIFO can be directed to the SAR portion (cells to be formatted into TDM streams), to the data cell portion (to be examined by the CPU), or to both. This is indicated by the RXD field in cells written into the RX_SAR output FIFO.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 +0h +2h +4h +6h GFC
GFC
b4 b3
b2 b1
b0 OAM CLP
VPI VCI[11:0]
VCI[15:12]
PTI
Payload Byte 0 Payload Byte 2
Payload Byte 1 Payload Byte 3
Payload Byte 45
+30h +32h +34h +36h +38h +3Ah +3Ch +3Eh
Payload Byte 44 Payload Byte 46
TXD
Payload Byte 47
RXD
RX Structure Pointer
Reserved
GFC: Generic Flow Control VPI: Virtual Path Identifier VCI: Virtual Circuit Identifier OAM: Management Cell. When this bit is set, the cell does not contain TDM bytes and is handled as an OAM cell. PTI: Payload Type Indicator. CLP: Cell Loss Priority (this bit is not examined by the MT90503). Payload Byte X: Payload byte in ATM cell (48 bytes total, numbered 0 to 47). TXD: TX_SAR Destination Field. "0000" = discard cell "0xx1" = Send to TXA port "0x1x" = Send to TXB port "01xx" = Send to TXC port "1001" = Treat as cell from RXA port "1010" = Treat as cell from RXB port "1100" = Treat as cell from RXC port others = reserved
RXD: RX_SAR destination field. "00" = reserved "x1" = Data Cell (write in RX Data Cell FIFO in external control memory) "1x" = RX_SAR CBR Cell (disassemble this cell with structure pointed to by RX Structure Pointer (Normal) field) RX Structure Pointer: Pointer to the RX_SAR Structure that will be used to process the current cell. Concatenated with "00000" to form a wp-bit address. (see RX_SAR structure). Note that RXA, RXB, and RXC input FIFOs do not contain any field beyond Payload Byte 47. Also note that the TX_SAR input FIFO does not contain any field beyond TXD. The TXD field is not written in any of the output FIFOs Note: The HEC field of the ATM cell is calculated and added for outgoing cells after the cell leaves the FIFO.
Figure 36 - Cell Format for cells in internal UTOPIA input and output cell FIFOs
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Zarlink Semiconductor Inc.
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Incoming Cell on UTOPIA Null Cell Elimination enabled VPI/VCI = '0' Null Cell Elimination disabled Into 4-cell input FIFO Cell discarded Prior to Cell Router
Data Sheet
A
(See Figure 39 on page 84)
Yes NNI = '1' No VPI = '1' No VCI = '1' Yes Yes
Replace VPI[11:8] in Cell Header
Replace VPI[7:0] in Cell Header
VPI/VCI Match & Mask (See Section 4.5.6)
No
OAM Cell
No No Route using Unknown nonOAM Cell Routing Yes OAM Cell No A, B = '1' No Route Cell According to NCR Bits Yes
Replcace VCI[15:0] in Cell Header
Yes Concatenate VPI/VCI Bits, read LUT (See Figure 40 on page 85)
Yes Route using Unknown OAM Cell Routing
Route according to OCR bits
Send A, B pulse to Clock Recovery
A
Figure 37 - Cell Router Flow
4.5.6
Match & Mask for cell routing
Cells are designated as "known" or "unknown" based on the result of a match & mask (configurable for each port). For a cell to be considered "known" all VPI/VCI bits whose corresponding mask bit is '1' must have the value contained in the corresponding bit of the match register. The match and mask registers for Port A are 0328h, 032Ah, 032Ch and 032Eh. Likewise the match and mask register for Port B are 0342h, 0344h, 0348h and 034Ah. For Port C, the registers are 0368h, 036Ah, 036Ch and 036Eh.
GFC | VPI | VCI (from cell header) 0010 10000000 00000000 10110010 Match Value 0000 00000000 00000000 10110010 Match Result (1 = Mismatch) 0010 10000000 00000000 00000000 Mask Value 0000 00111111 00000000 11111111 Mask Result (1 = mismatched cell) 0000 00000000 00000000 00000000 Result Routed according to LUT entry
0010 10000000 00000000 10110110 0000 00000000 00000000 10110010 0010 10000000 00000000 00000100 0000 00111111 00000000 11111111 0000 00000000 00000000 00000100
Routed as unknown cell
For each bit, result = (match XOR header) AND mask
Figure 38 - Match & Mask Example In addition, the Cell Router can be configured to eliminate null cells (those with VPI = 0 and VCI = 0). For the purpose of null cell elimination, the NNI can be included on a per-port basis (see registers 0300h and 0302h).
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Data Sheet
Unknown non-OAM cells and/or unknown OAM cells can be discarded or directed to one or more output FIFOs. All unknown non-OAM cells from a port are discarded or directed to the same location(s) and all unknown OAM cells from a port are discarded or directed to the same location(s). Unknown cells can be directed differently for each port on which they were received. Unknown cells cannot be sent to the SAR portion of the RX_SAR. The routing of unknown cells is set in registers 03A2h and 03A4h. Known cells are handled according to the LUT (Look-Up Table) entry for the cell's VPI/VCI.
4.5.6.1
Look-Up Tables Entries
LUT entries direct cells with known VPI/VCIs to either be discarded or placed in one or more of five possible destinations: the four output FIFOs and the data cell FIFO in external control memory, by way of the RX_SAR FIFO. OAM cells can be directed independently of non-OAM cells with the same VPI/VCI. OAM cells cannot be directed to the SAR portion of the RX_SAR. LUT entries can be either 4- or 8-bytes long (short or long LUT entries, set in register 302h). All look-up table entries in all three LUTs are the same size. 8-byte entries are only required if header translation is to be performed for one or more VCs. Cells undergoing header translation have their NNI bits, the remaining VPI bits and/or the VCI bits replaced by the corresponding bits in the LUT entry and are then either discarded or sent to one or more of the possible destinations. VCs that undergo header translation are not directed to the SAR portion of the RX_SAR. Clock recovery information can be gathered from up to two VCs by setting bit A in one LUT entry and bit B in the same or another LUT entry. A maximum of one VC can have bit A set and a maximum of one VC can have bit B set.
Non-header translation LUT Entry Format
b15 b14 b13 b12 b11 b10 b9 b8 +0 +2 0 0 0 A B
b7 b6 NCR
b5
b4 b3
b2
b1
b0
OCR
RX Structure Pointer
LUT Entry Format for Header Translation
b15 b14 b13 b12 b11 b10 b9 b8 +0 +2 +4 +6 NNI VPI VCI A VPI[11:8] B VPI[7:0] VCI[11:0]
b7 b6
b5
b4 b3
b2
b1
b0
NCR
OCR VCI[15:12]
Reserved
Note: If chip is configured for long LUT entries, non-header translation LUT entries are followed by two reserved words.
NNI: When '1' the VPI[11:8] field in each cell for this LUT entry will be replaced by the VPI[11:8] contained in this entry. VPI: When '1' the VPI[7:0] field in each cell for this LUT entry will be replaced by the VPI[7:0] contained in this entry. VCI: When '1' the VCI[15:0] field in each cell for this LUT entry will be replaced by the VCI[15:0] contained in this entry. A, B: Adaptive/SRTS Clock Recovery VC A or VC B. Only one VC can have bit A set. Only one VC can have bit B set. NCR: Normal (non-OAM) Cell Routing '00000' = discard 'xxxx1' = send to TXA port 'xxx1x' = send to TXB port 'xx1xx' = send to TXC port 'x1xxx' = send to data cell FIFO (in external control memory) via the RX_SAR '1xxxx' = send to SAR portion of the RX_SAR OCR: OAM Cell Routing '0000' = discard 'xxx1' = send to TXA port 'xx1x' = send to TXB port 'x1xx' = send to TXC port '1xxx' = send to data cell FIFO (in external control memory) via the RX_SAR
Figure 39 - Short and Long Look-Up Table Entries
4.5.6.2
LUT Addressing
A LUT base address exists for each of the three ports (registers 0320h, 0340h, 0360h). The LUT base addresses for two or more ports can be the same. An identifier for a VC is created by concatenating any number of LSBs from the VPI and LSBs from the VCI, to a maximum of 16 bits. The number of VCI bits used is programmed in registers 0324h, 0344h and 0364h for Port A, B, C respectively. The total number of bits in the identifier is programmed in registers 0322h, 0342h and 0362h for Port A, B and C respectively.The identifier is then appended with either two or three zeros (for either short or long LUT entries).
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Data Sheet
Finally, this value is used as the byte-pointer to the LUT entry, offset from the LUT base address for that port.
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VPI VCI vci_na (reg. 0324h) = 5 VCI Bits num_vci_vpi_bits (reg. 322h) = 16 Concatenated VPI and VCI b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
..............
Notes: This example is for port A and for short LUT entries. All three ports have independent parameters (vci_n, num_vpi_vci_bits, LUT Base Address). Identifier is a pointer, offset from the LUT Base Address, to the first byte of the LUT entry. Identifier is appended with either "00" (short LUT entries) or "000" (long LUT entries). LUT Base Address comprises bits 19:4 of the base address. "0000" is appended. LUT Entry Address represents a byte address
.....................
identifier
0 0
b15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b0
LUT Base Address (reg. 0320h)
0000
LUT Entry Address
b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Figure 40 - VPI/VCI Concatenation and LUT Entry Address Example
4.5.6.3
UTOPIA Clocks
Each of the three ports must have a clock to operate the receive interface and a clock to operate the transmit interface. Two or more clocks may have the same source. These clocks can either be input to the MT90503 from an external source or output from the MT90503, from one of three internal UTOPIA clocks. For each port the transmit clock and receive clock must be configured to be either both input or both output. An exception is Port C where both transmit clock and receive clock must be input only. The source of the each of the three internal UTOPIA clocks can be one of eight clocks: mclk, fast_clk, or any of the six UTOPIA clocks (rxa, rxb, rxc, txa, txb, and txc). The selected clock is divided by n, an integer from 1 to 16, and can be inverted. Other parts of the UTOPIA module, including the look-up engine, the TX_SAR portion and the RX_SAR portion operate off of mclk.
4.5.7
LED Operation
The UTOPIA module generates two LED signals for Port A (pins D2, H5) and two LED signals for Port B (pins W5, T5) in order to indicate the status of the A and B ports. The status conditions are: idle, presence of traffic, or PHY alarm. When a port is in an idle state, both its LEDs are illuminated. If RX traffic (other than null cells) is flowing, then the RX LED for that port will flash; If TX traffic (other than null cells) is flowing, then the TX LED for that port will flash. If a PHY alarm is detected, the TX LED is on and the RX LED is off. The polarity of the LED signals is active-low, i.e., a `0' will turn the LED on. The frequency of the LEDs is programmed in registers 0120h and 0122h while the LEDs are enabled in register 0302h.
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Zarlink Semiconductor Inc.
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One of three UTOPIA clock generators
Data Sheet
mclk Inversion fast_clk rxa_clk rxb_clk rxc_clk txa_clk txb_clk txc_clk
One of six UTOPIA Clocks
utopia_clk_1 Divider by n (n=1 to 16)
utopia_clk_1 utopia_clk_2 utopia_clk_3 rxa_clk
Figure 41 - UTOPIA Clock Generation
4.5.8
UTOPIA Flow Control
The UTOPIA module contains the ability to prevent cells in the 4-cell input FIFOs (RXA, RXB, RXC, and TX_SAR) from being handled by the UTOPIA module in the case that the 32-cell output FIFOs (TXA, TXB, TXC, and RX_SAR) exceed programmable levels. An input FIFO will be blocked when the level of any output FIFO exceeds the level set for that combination of output FIFO and input FIFO. The levels can be set independently to 1 to 31 cells or to 0, which means no flow control will be exerted (see registers 0338h-033Ah, 0358h-035Ah, 0378h-037Ah). Cell arrival counters and cell departure counters for each port, stored in registers (0330h-0336h, 0350h-0356h, 0370-0376h, 0390-0396h), are used to monitor the fill levels of each output FIFO.
4.5.9
External Interface Signals
Due to the different possible configurations of the UTOPIA ports, the functions of some pins change, depending on the configuration. Some unused data pins when port A and/or port B are in 8-bit mode become general purpose inputs and/or outputs. When Level-2 addressing is in place for port A, portions of the port B data buses are used for as port A addressing pins. The function of the clav (cell available) and enb (enable data transfer) pins alternate when the port is in ATM mode or PHY mode (Figure 42 on page 87). Please note that the I/O direction of the pins remains the same.
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PHY Device
Data Sheet
MT90503 - ATM Mode
ATM Device rxclk rxenb rxclav
MT90503 - PHY Mode txa_clk (H3) txa_enb (J5) txa_clav (H2) txa_soc (N2) txa_d (N4 . . .) txa_par (N3)
txclk txenb txclav txsoc txdata txpar
txa_clk (H3) txa_enb (H2) txa_clav (J5) txa_soc (N2) txa_d (N4 . . .) txa_par (N3)
rxsoc rxdata rxpar
rxclk rxenb rxclav rxsoc rxdata rxpar
rxa_clk (C6) rxa_enb (B6) rxa_clav (A6) rxa_soc (H4) rxa_d (G3 . . .) rxa_par (G2)
txclk txenb txclav txsoc txdata txpar
rxa_clk (C6) rxa_enb (A6) rxa_clav (B6) rxa_soc (H4) rxa_d (G3 . . .) rxa_par (G2)
Port A, ATM Mode
Port A, PHY mode Figure 42 - External UTOPIA Interface
4.6 4.6.1
Clock Recovery Module Overview
The purpose of the clock recovery module is to synchronise the TDM clock domain of the MT90503 with other devices on the network through information transmitted across the ATM link. Clock recovery is necessary only when the MT90503 is operating as the TDM clock master. The clock recovery system is composed of several sub-components:
4.6.1.1
Two Point Generation Modules
The point generation modules permit SRTS and/or adaptive clock recovery to be performed by the MT90503. The two modules provide the flexibility to have a back up clock recovery process operating from another VC and/or of the complementary type. These modules generate points which are written to control memory and subsequently used by the clock recovery algorithm.
4.6.1.2
One SRTS (synchronous residual time stamp) Generating Module
The SRTS generating module, is employed to generate the 4-bit outgoing RTS value.
4.6.1.3
Three Integer Divisor Clock Modules
The integer divisor clock (idclk) modules are designed to manipulate any incoming or internal clocks and produce an 8kHz idclk. They provide the flexibility of inverting the clock before or after division, option of setting the duty
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Zarlink Semiconductor Inc.
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Data Sheet
cycle to 50%, 16-bit division and checking of the frequency (within a desired range). Along with the idclk_loss signals, idclk's are suited to being sent to an external PLL.
4.6.1.4
Two Precise Clock Modules
The precise clock (pclk) modules are used to divide mclk down to pclk_a and pclk_b. Each module has a pclk_loss indicator which can be employed in tandem with the pclk signal to be routed to an external PLL. The division of mclk is performed with a 16-bit integer and a 16-bit fraction, allowing for precise specification of the pclk frequency. These modules are ideally suited to being programmed by the clock recovery algorithm to generate the recovered clock.
4.6.1.5
Eleven Multiplexers
The 11 multiplexers are: recov_a to recov_h, ct_netref1, ct_netref2 and local_netref_16m. recov_a through recov_h and ct_netrefx are general I/O pins. Local_netref_16m is an internal node, used as the master clock for the TDM section of the MT90503.
4.6.2
Multiplexers
There are eleven multiplexers (see Table 28, "Source Selection," on page 89) with 36 possible inputs each (see Table 29, "idclk_a Register," on page 91): Signal recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref1 ct_netref2 local_netref_16m Address 0860h 0860h 0862h 0862h 0864h 0864h 0866h 0866h 0868h 0868h 086Ah Bits 13:8 5:0 13:8 5:0 13:8 5:0 13:8 5:0 13:8 5:0 5:0
Table 27 - Multiplexer Registers
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Zarlink Semiconductor Inc.
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mclk pclk_a pclk_b pclk_valid_a pclk_valid_b idclk_a idclk_b idclk_c idclk_valid_a idclk_valid_b idclk_valid_c recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref1 ct_netref2 ct_c8_a ct_c8_b ct_c8 ct_frame_a ct_frame_b ct_frame '0' '1'
Output pins generated: recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref1 ct_netref2 local_netref_16m
Data Sheet
Figure 43 - Multiplexer
Source Select Number 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100
Hex Values 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C
Source Logical 0 Logical 1 Tri-state Ground Vcc high-impedance Reserved pclk_a pclk_valid_a pclk_b pclk_valid_b idclk_a idclk_valid_a idclk_b idclk_valid_b idclk_c precise clock precise clock valid precise clock precise clock valid integer divisor clock
Description
integer divisor clock valid integer divisor clock integer divisor clock valid integer divisor clock
Table 28 - Source Selection
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Zarlink Semiconductor Inc.
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Source Select Number 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 Hex Values 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_c8 ct_c8_a ct_c8_b ct_frame ct_frame_a ct_frame_b ct_netref1 ct_netref2 ref_vca ref_vcb phy_alm_a phy_alm_b mclk Source idclk_valid_c Description integer divisor clock valid Reserved Reserved external I/O pin external I/O pin external I/O pin external I/O pin external I/O pin external I/O pin external I/O pin external I/O pin active clock: ct_c8_a or _b TDM clock TDM clock active clock: ct_frame_a or _b TDM clock TDM clock TDM clock TDM clock cell arrival on VC A cell arrival on VC B PHY Alarm UTOPIA A PHY Alarm UTOPIA B master clock
Data Sheet
Table 28 - Source Selection (continued)
4.6.3
Integer Divisor Clocks (idclk)
There are three idclk modules in the MT90503. Each module consists primarily of a 16-bit integer clock divider, but also has several clock manipulation circuits. These modules have the ability to flag an interrupt (if enabled - 0884h, 08A4h, 08C4h) if the input frequency is above or below a desired range, invert the clock's polarity (before and after division) and set the percentage duty cycle to 50%. idclk_loss_x signals the loss (or incorrect frequency) of an input synchronisation clock, allowing the clock to easily be output to an external PLL. idclk_a is configured in the register range of 0880h-0894h as described in Table 29.
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Data Sheet
These modules are ideally suited to dividing down the highly accurate reference clock (fn) required when performing SRTS clock recovery.
Register 0880h 0880h 0880h 0880h 0880h 0880h 0882h 0884h 0886h 0888h 0888h 0888h 088Ah 0890h 0892h 0894h Bits [0] [1] [2] [3] [4] [13:8] [5:0] [5:0] [5:0] [5:0] [6] [7] [15:0] [15:0] [15:0] [15:0] ext_loss_source_select ext_loss_source_polarity output_loss_polarity clk_div freqchck_div freqchck_max_mclk_cycles freqchck_min_mclk_cycles Name divisor_load_now divisor_reset even_duty_cycle_select input_invert_select output_invert_select input_source_select set to load new value 0 for reset, 1 for normal operation when 1, 50% duty cycle is generated invert clock before dividing invert clock after dividing see Table 28 status registers interrupt enabling manual setting of status registers external output of input clock status. See Table 28. if set to '1', source loss is active high if '1' output loss is active high denominator of clock divider denominator of frequency check divider max # of mclk's between rising edges of the input clock divided by freqchck_div, if failure occurs, freq_too_low (0882h) will be set. min # of mclk's between rising edges of the input clock divided by freqchck_div, if failure occurs, freq_too_high (0882h) will be set. Description
Note: idclk_b and idclk_c have a corresponding set of registers in the ranges of 08A0h - 08B4h and 08C0h - 08D4h respectively.
Table 29 - idclk_a Register
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Zarlink Semiconductor Inc.
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mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref
Data Sheet
0880h [13:8]
0880h [2]
0880h [3] Divider 088Ah, 0880h[1:0]
0880h [4] idclk_a
Clock Frequency Checker 0890-0894h
50% Duty Cycle Modifier 0880h[2] idclk_valid_a
mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref
08A0h [13:8]
08A0h [2]
08A0h [3] Divider 08AAh, 08A0h[1:0] 50% Duty Cycle Modifier 08A0h[2] Clock Frequency Checker 08B0-08B4h
08A0h [4] idclk_b
idclk_valid_b
mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref
08C0h [2] 08C0h [13:8]
08C0h [4] 08C0h [3] Divider 08CAh, 08C0h[1:0] 50% Duty Cycle Modifier 08C0h[2] idclk_valid_c idclk_c
Clock Frequency Checker 08D0-08D4h
Figure 44 - Integer Clock Processor
4.6.4
Precise Clocks (pclk)
The MT90503 has two digital PLL (pclk) modules. Using mclk as a source, the module will divide it with a 16-bit integer and optional 16-bit fraction. The 16-bit fraction allows more precise specification on the output frequency. Using the optional 16-bit faction in a typical configuration, mclk = 80MHz, pclk_int_a = 10 000 and pclk_a = 8kHz, will increase the precision from 100 ppm to 1.5 ppm. Also, using the fractional divider will reduce the maximum jitter to one mclk period (12.5ns for 80MHz mclk). Set pclk_frc to 0 if no jitter insertion by the pclk module desired. The divider can be programmed dynamically and has a maximum response time of 125s.
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The following registers are applicable: Register 0820h[5] 0820h[6] 0820h[7] 0830h 0832h 0820h[5] 0840h[6] 0840h[7] 0850h 0852h Name adapsrts0_pclk_loss adapsrts0_pclk_divisor_load_now adapsrts0_pclk_divisor_reset adapsrts0_pclk_div adapsrts0_pclk_frc adapsrts1_pclk_loss adapsrts1_pclk_divisor_load_now adapsrts1_pclk_divisor_reset adapsrts1_pclk_div adapsrts1_pclk_frc indicates state of clock Description
Data Sheet
when set, pclk_div and pclk_frc are loaded into digital PLL. when '0' digital PLL is in reset state integer divider of pclk_a fractional divider of pclk_a indicates state of clock when set, pclk_div and pclk_frc are loaded into digital PLL. when '0' digital PLL is in reset state integer divider of pclk_b fractional divider of pclk_b
Table 30 - pclk registers The following equation illustrates the derived frequency of pclk from mclk:
f mclk f pclk = ----------------------------------------pclk frc pclk div + ---------------65536
4.6.5
Point Generation
The function of the point generation module is to place points in external memory which have been generated by either the SRTS or Adaptive clock recovery methods. These points express the rates of the master device's TDM clock (through a time stamp or the cell rate), the rate of the slave (performing the clock recovery) device's master clock and the rate of the slave device's pclk. This allows the clock recovery algorithm to evaluate the respective rates and make corrections to the pclk in order to synchronise with the master device. There are two point generation modules. Each can be configured for SRTS or adaptive clock recovery. The two modules each have a separate point generation process, separate timing reference and each is associated with one pclk module (i.e. pclk_a with adapsrts0 and pclk_b with adapsrts1). This allows switching between clock recovery types and/or sources on the fly. The A and B bits of the UTOPIA look-up table determine which VC generates ref_vca and ref_vcb (see section 4.5.6.1 on page 84). Register 0820h 0820h Bits 0 1 Name adaptive_enable rx_srts_enable Module1 A S Description '1' activates adaptive clock recovery '1' activates SRTS clock recovery
Table 31 - adapsrts0 Registers2
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Register 0820h 0820h 0820h 0822h 0822h 0822h 0822h 0822h 0822h Bits 2 3 4 0 1 2 3 4 5 Name ignore_crc ignore_parity ignore_seq_num aal1_crc_error aal1_bad_parity single_cell_lost multi_cell_lost cell_misinserted timeout_flag Module1 B B B B B B B B B Description '1' ignores CRC of AAL1 byte '1' ignores parity bit of AAL1 byte
Data Sheet
'1' ignores sequence number of AAL1 byte status bit indicating CRC error status bit indicating parity error status bit indicating single cell loss status bit indicating multiple cell loss status bit indicating a cell misinsertion error status bit indicating interval since last cell exceeds time_out_period (0828h) (reset when timeout ceases) status bit indicating the interval between two cells has exceeded the time_out_period (0828h) status bit indicating the interval between remote SRTS values received was too short and one was lost status bit indicating the interval between local SRTS values received was too short and one was lost Interrupt Enables
0822h 0822h
6 7
timeout_pulse rx_srts_remote_overflow
B S
0822h
8
rx_srts_local_overflow
S
0824h 0826h 0826h 0828h 082Ah 082Ch
[8:0] [5:0] [13:8] [15:0] [7:0] [15:0] ref_input_select rx_fnxi_input_select time_out_period adap_pnt_elim_x srts8m8c_div_p A S B A S
timing reference (usually ref_vca or ref_vcb), see Table 28. selects fnxi input, see Table 28. time-out period between two cells (units - 1024 mclk cycles) "keep 1 point out of X" and write to external memory pclk must be divided by K in order to match the interval of 8 SRTS carrying cells, where K = P/Q, P is normally the number of frames in the scheduler, i.e. 375 for fully filled structured AAL1 Q is the number of channels open
082Eh
[15:0]
srts8m8c_div_q
S
Table 31 - adapsrts0 Registers2 (continued)
1. adaptive relevant register, S - SRTS relevant register, B - relevant to both 2. A corresponding set of registers exists for adapsrts1 from 0840h - 084Eh.
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From Registers
Data Sheet
pclk_div pclk_frc
load_divisor_now
Precise Clock Generator
ref_vca pclk ref_vcb
pclk Counter
mclk Counter
ref_input_select pclk_integer[31:0] pclk_fraction[15:0] mclk_counter[31:0]
AAL1 byte
Elimination of lost_cell_pulse cells with bad CRC or parity, Cell Counter compensation for valid_cell_pulse lost cells
cell_counter [31:0]
Point Generation Process
Write Points to External Control Point Elimination Memory (keeps 1 point out of x cells)
Time-out Detection
Figure 45 - Adaptive Clock Recovery
4.6.6
Adaptive Clock Recovery
Adaptive clock recovery is a method which generates a clock based on the rate at which AAL1 cells are arriving. The device acting as the master does not have to structure its cells differently or add any information, it simply transmits CBR data in AAL1 cells. The slave device performs the adaptive clock recovery, based on a clock recovery algorithm using points placed in external memory by the point generation module. To perform adaptive clock recovery, the point generation module of the MT90503 is normally configured with the cell arrival event (ref_vca or ref_vcb) as its timing reference (source 0x20 or 0x21 of Table 28, "Source Selection," on page 89). The VC's which are defined as vca and vcb are recorded in the UTOPIA LUT (see Figure 39 on page 84). The input multiplexer gives the flexibility to use any clock desired. The cell arrival event is received directly from the UTOPIA look-up module. The look-up engine generates a VC-specific pulse and passes on the AAL1 byte of the received cell. The AAL1 byte is composed of a sequence number (SN), CRC-3 sequence number protection (SNP) and a parity bit. The adaptive module checks for CRC and parity errors. If errors are found, the cell is ignored and the appropriate bit of register 0822h or 0842h is flagged. The sequence number is also verified to determine if cells have been lost. Single cell losses can be compensated for and the single_cell_lost register bit (0822h or 0842h [2]) will be set. Multiple cell losses cannot be compensated, but will be flagged as either multi_cell_lost (0822h or 0842h [3]) or cell_misinserted (0822h or 0842h [4]).
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AAL1 Byte
Data Sheet
Parity OK and CRC OK Yes
No
Discard Cell
SN = Last SN + 1
Yes
Generate 'ref_vcx' pulse
No
SN = Last SN + 2
Yes Generate two 'ref_vcx' pulses (lost cell detected)
No
SN = Last SN - Yes 1 & Last SN = SecLast SN + 2 No Discard Cell (multiple cell loss detected)
Discard Cell (misinserted cell detected)
Figure 46 - Adaptive Cell Reception Flow The point recording portion of the module records three fields. The 'number of the cell' is a 32-bit field, the 'number of mclk cycles' counted at time of cell arrival is a 32-bit field and the 'number of pclk cycles' counted when the cell received is a 48-bit field composed of a 32-bit integer and 16-bit fraction. This information, from the three counters (cell, mclk and pclk), 112 bits in total, is written to external control memory in a circular buffer reserved for clock recovery information. (See External Memory Point Format on page 98.) Ratios of this data are compared by the clock recovery algorithm to the desired ratios and correspondingly, corrections are made to the pclk frequency dividers. It is possible to eliminate some of the timing reference cells sent to memory. This may be done in order to conserve processing power. It is especially useful if the clock recovery VC has a high number of channels (i.e. a high rate of cell arrival). The 8-bit registers, adap_pnt_elim_x (082Ah and 084Ah) can be programmed to "keep one point out of X". Each adaptive module has its own associated pclk generator, allowing the wander of each VC to be tracked with respect to the pclk frequency.
4.6.6.1
SRTS Clock Recovery
The Synchronous Residual Time Stamp (SRTS) method of clock recovery is standardised in ITU-T I.363.1, ANSI T1.630 and Bellcore's patent1 (U.S. Patent 5 260 978 (11/93)). The SRTS method uses a stream of residual time stamps (RTS) to express the difference between a common reference clock (fn) and a local service clock (fs - derived from the local TDM clock, ct_c8_x).
1. Zarlink has entered into an agreement with Bellcore with respect to Bellcore's U.S. Patent No. 5,260,978 and Zarlink's manufacture and sale of products containing the SRTS function. However the purchase of this product does not grant the purchaser any rights under U.S. Patent No. 5,260,978. Use of this product or its resale as a component of another product may require a license under the patent which is available from Bell Communications Research, Inc., 445 South Street, Morristown, New Jersey 07960.
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Data Sheet
The point generation modules can both be configured for SRTS clock recovery and receive data simultaneously from 2 VCs. Like adaptive clock recovery, the data is retrieved from the UTOPIA look-up module. The SRTS values however, are spread over 8 cells. As in the adaptive mode, CRC errors, parity errors and missing cells are reported to their respective registers (0822h & 0842h [4:0]). This component of the SRTS recovery that receives SRTS data on a VC from an outside source generates "remote" data The SRTS clock recovery method requires an accurate external reference clock (fn) (e.g., a stratum 3 clock). This clock drives the 4-bit counter fnxi_cnt. This count is compared to a count driven by the precise clock digital PLL. In order to match the interval of 8 SRTS carrying cells, pclk (8 kHz) must be multiplied by K. K is proportional to the number of frames in the scheduler (P) (375 for fully filled structured AAL1) and inversely proportional to the number of channels open (Q) (respectively of registers 082Ch and 082Eh for point generation module 0 (adapsrts0)). i.e., K=P/Q. This component of the SRTS clock recovery that compares the pclk generated clock with that of the fnxi clock generates "local" data. These "local" and "remote" values are written to external memory for the CPU to access.
pclk
Input* 1024
8.192 MHz
Input/ ((P * 1024) / Q)
8 Cell Pulse
RX SRTS Value Writter (to external memory)
To external control memory
Local
recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h idclk_a idclk_b idclk_c
fnxi
fnxi_cnt[3:0]
ref_vcx AAL1 Byte
Elimination of Cells that have bad CRC/Parity
SRTS Value write_now concatenation srts_value[3:0] Lost and Misinserted Cell bad_srts_value Compensation
RX SRTS Value Writter (to external memory)
To external control memory
Remote
Time-out Detection
Figure 47 - Rx SRTS Clock Recovery Module
4.6.7
SRTS Transmission
Similar to the SRTS receive side, the generation of SRTS data must take into account the number of frames in the scheduler (P of register 0818h) and the number of channels in the VC (Q of register 081Ah). A single VC may be used to carry SRTS or the SRTS values may be broadcast on multiple VCs. These VCs must, however, be of the same format, consistent with the master SRTS VC. These VC's are configured in the Tx SAR (see Table 22 on page 65).
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ct_c8_a ct_c8_b ct_c8 Input/ ((P * 1024) / Q) 8 Cell Pulse 5 Value SRTS Buffer
Data Sheet
change srts To TXSAR
recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h idclk_a idclk_b idclk_c
fnxi
fnxi_cnt[3:0]
Figure 48 - Tx SRTS Clock Recovery Module
Register 0810h 0810h 0810h 0812h 0812h 0814h 0818h 081Ah
Bits 0 [1:2] [8:13] 0 1 [0:1] [0:15] [0:15]
Name enable bus_clk_sel fnxi_input_select overflow underflow '1' enables Tx SRTS
Description
source of timing: '10' - ct_c8_a,'11' - ct_c8_b,'0x' - follows active clock, ct_c8_a or _b selects source of fnxi see Table 28 set if values sent by Tx SRTS is greater than the number of values read by the Tx SAR set if the number of Tx SRTS values is less than that read by the Tx SAR Interrupt Enables
srts8m8c_div_p srts8m8c_div_q
P = number of frames in the scheduler Q = number of channels open
Table 32 - Tx SRTS Registers
4.6.8
External Memory Point Format
Figure 49 on page 99 indicates the format of the circular buffers in external memory that contain SRTS and adaptive point information. In adaptive clock recovery, a point is the information pertinent to the reception of a single cell. In SRTS, a point is the information corresponding to reception of an SRTS value (gathered over eight cells). If the received SRTS value is corrupt (due to errors in the received cells) the valid bit (V) will be 0.
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b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 V V V RX SRTS RX SRTS RX SRTS Local SRTS Local SRTS Local SRTS Reserved
Data Sheet
Note: The base address and size of each buffer is configurable in registers 090Eh 0912h, 091Ch - 0920h.
V Adaptive Point Buffer +0 +10 +20 +30 +40 Point 0 Point 1 Point 2 Point 3 Point 4
RX SRTS
Local SRTS b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 +A pclk Counter Integer [31:16] pclk Counter Integer [15:0] pclk Counter fraction [15:0] mclk Counter [31:16] mclk Counter [15:0] Cell Counter [31:16] Cell Counter [15:0]
Point N
+C +E
Figure 49 - Clock Recovery Information Buffers
Field V RX SRTS Local SRTS
Name of Field Valid Bit Remote SRTS value Local SRTS value
Bits Used b12 b11:b8 b3:b0
Description Set if the accompanying RX SRTS value is valid The 4-bit SRTS value from the incoming ATM cells on the designated VC. The 4-bit SRTS value calculated based on pclk and fnxi
Table 33 - SRTS Pointer Buffer, Field Description
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5.0
5.1
Data Sheet
Memory
Memory Overview
The MT90503 requires external memory for two purposes: control and data memory. The control memory contains information required for: TX_SARs and RX_SARs control structures, transmission schedulers, look up values to map VCs to RX structures. The control memory also stores data cell FIFO's. CAS buffers and clock recovery data is also stored in the control memory. The data memory is employed to store network traffic data for a maximum of 2048 bi-directional TDM channels. The MT90503 interfaces with the external Data SSRAM via the following pins: 19 address pins (dmem_a), 4 memory bank/chip selection pins (dmem_cs), 16 data pins, (dmem_d), 2 parity pins (dmem_par), 1 R/W(low) pin used for late write memories (dmem_rw), 2 data memory byte write select pins (dmem_bws) and a memory clock (mem_clk). The external Control SSRAMs interface pins: 19 address pins (cmem_a), cmem_a[18] can be configured as a: memory bank/chip selection pin (cmem_cs[1]) or an address pin cmem_a[18], 1 dedicated memory bank/chip selection pin (cmem_cs[0]), 16 data pins, (cmem_d), 1 R/W(low) pin used for late write memories (cmem_rw), 2 control memory byte write select pins (cmem_bws). The data memory supports up to 4 memory banks up to 512 k words per bank determining a data memory limit of 4 MB. The data memory clock speed gamut is 40 MHz to 80 MHz. Note: recommended mem_clk speed is 80 MHz. The option of a reduced memory capability is also supported. The following SSRAM sizes can be employed: 128 kB, 256 kB, 512 kB and 1 MB. The data bus consists of 18 data bits where two data bits are dedicated as parity bits. The parity bits are used to detect underruns in the circular buffers generated on the ATM link and data error detection. The parity check can be disabled to permit non-parity memory compatibility. The MT90503 supports 1, 2, 3 or 4 banks of external memory, each bank having a total capacity ranging from 64 k x 18 bits to 512 k x 18 bits. Therefore the MT90503 can operate with external memory ranging from 128 kB to 4 MB. The above data memory configuration is initialised via: Data Memory Parity 0 Register, Data Memory Parity 1 Register and Data Memory Configuration Register (0248h, 024Ah & 024Ch respectively). The control memory maximum capacity is 512 k words and supports 2 memory banks. The reduced memory capability is supported in the same manner as the data memory. However, if all 19 address bits are employed then the use of 1 memory bank is permitted. Therefore the MT90503 can operate with external control memory ranging from 128 kB to 1 MB. The MT90503 dose not use the parity bits supplied by the control memory. Parity bits can be generated within the MT90503 and are used for error detection. The above control memory configuration is initialised via: Control Memory Parity 0 Register, Control Memory Parity 1 Register and Control Memory Configuration Register (0240h, 0242h & 0244h respectively). The MT90503 supports both Pipelined and Flow Through SSRAM employing either: `normal' or `Zero Bus Turnaround' (ZBT) operation. When PECL clock is employed `Late-Write' is supported in `normal' operation. The memory clock (mem_clk) interface must be configured to either PECL or TTL. The interface can be initialised via the `CPU Control Register' address 0100h. The external memory controller can interface with several types of SSRAM, but they must support synchronous bus enabling. The SSRAM chip must only enable its data output buffers one cycle after a read (two for pipelined SSRAM), irrespective of the state of the asynchronous output enable pin. A read is indicated by mem_rw high and the appropriate mem_cs asserted. The SSRAM can be a registered input type (Synchronous, Synchronous Flow through or Synchronous Burst) or a registered input/output type (Synchronous pipelined). Although the MT90503 uses synchronous access feature of the memory, it does not use the burst access feature of the memory. Specific Synchronous SRAM devices may require a turnaround cycle with respect to the bidirectional data bus. The MT90503 can be configured to insert a turnaround cycle between read access and write access. A turnaround cycle can be inserted between read access and read access to other memory banks. The turnaround cycle configuration is initialised via: Control Memory Configuration Register and Data Memory Configuration Register (0244h & 024Ch respectively). It should be noted that turnaround cycles restrict the memory bandwidth and therefore the operation MT90503. Maximum throughput is achieved with full clock speed on MCLK and without pipelined synchronous RAM and turnaround cycles.
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5.2 Memory Map
Data Sheet
The location of the absolute starting and ending addresses of the internal and external memories are shown in Table 34 - MT90503 Memory Map. The complete set of internal registers is listed in section 5.5 "Detailed Register Description", on Page 99.
Start Address 0100h 0200h 0300h 0400h 0500h 0600h 0700h 0800h 0900h 0A00h 1000h 1400h 1800h 1C00h 2000h 3000h 4000h 5000h 8000h 200000h 400000h
End Address 01FEh 02FEh 03FEh 04FEh 05FEh 06FEh 07FEh 08FEh 09FEh 0AFEh 10FEh 14FEh 18FEh 1CFEh 27FEh 33FEh 43FEh 53FEh BFFEh 2FFFFEh 7FFFFEh CPU Registers Main Registers UTOPIA Registers TDM Registers TX_SAR Registers Scheduler Registers RX_SAR Registers Clock Registers
Name
Miscellaneous Registers H.100 Registers TX SAR Input FIFO UTOPIA Port A Input FIFO UTOPIA Port B Input FIFO UTOPIA Port C Input FIFO RX SAR Output FIFO UTOPIA Port A Output FIFO UTOPIA Port B Output FIFO UTOPIA Port C Output FIFO TDM Channel Association Memory External Control Memory External Data Memory
Table 34 - MT90503 Memory Map
5.3
Memory Controllers
Two memory controllers for external SSRAM exist in the MT90503: one for data memory and one for control memory. The memory controller blocks of the MT90503 reside between the internal blocks and the external memory. They receive memory access requests from the internal blocks (TDM, TX_SAR, RX_SAR, and CPU interface modules) and service them by reading data from, or writing data to, the external memories.
5.3.1
Data Memory
The data memory contains * TX/RX circular buffers: one per channel, each with a programmable size of 128, 256, 512, or 1024 words.
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Data Sheet
The data memory can be up to 4 MB in size. This allows 2048 TDM channels to each have a maximum-size circular buffer: 2048 TDM channels * 2048 bytes/channel = 4 MB. A parity bit, necessary to detect underruns on incoming TDM data, can be disabled, allowing non-parity memory to be used. The parity bit, when enabled, is also used for error detection. The data memory can be distributed between one and four banks. 16 to 19 address bits are required to access the 128 KB to 1 MB banks of data memory.
5.3.2
Control Memory
The control memory contains * * * * * * * * * TX control structures: one per VC, minimum of 12 words each, maximum of 48 KB total RX control structures: one per VC, minimum of 14 words each, maximum of 56 KB total Transmit event schedulers: up to fifteen, typical sizes are 6 to 150 KB per enabled scheduler Look-up table: three LUTs, each with one entry per known VC, 4 or 8 bytes per entry Data cell FIFO: two FIFOs, each programmable in length from 4 to 16384 cells, 32 words per cell CAS change buffers: 1 to 32768 words in size Silent tone buffers: 1 to 32768 words in size Clock recovery point buffers: 9216 words in size Error message buffer: programmable length of 0 to 65536 error report structures, 4 words per structure.
The control memory can be up to 1 MB in size. A parity bit is used for error detection. The control memory can be distributed in either one or two banks. As with the data memory, 16 to 19 address bits are employed; when 19 address bits are used, only one memory bank can be supported.
5.3.3
Data Memory Controller
There are five agents which interact with the data memory controller: TX_SAR, RX_SAR, TDM transmit, TDM receive, and CPU (through the CPU interface). Of these five agents, all but the CPU send their accesses to their internal cache, one for each agent, from which the data is written into the data memory when the data memory bus is available. The internal caches are capable of buffering up to 128 words each. Agent TX_SAR RX_SAR TDM transmit TDM receive CPU Access types Reads Writes Writes Reads Reads and writes
Table 35 - Types of Data Memory accesses for each agent The CPU has the highest priority on the write accesses and writes whenever it is flagged to do so. The priority arbitration used for accesses to the CPU is described in more detail the CPU module section (See 4.1 on page 34). The memory controller generates the CRC-32 needed for each AAL5-VTOA cell.
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5.3.4 Control Memory Controller
Data Sheet
Unlike the data memory controller, the control memory controller does not contain internal caches. Agents' read/write requests are granted on a cycle-by-cycle basis and each agent waits until its request has been completed. Each agent has its own access port allowing it to communicate address, data, r/w, and write enable information with the memory controller. The agents are identified in Table 36 - on page 103. Arbitration between the agents for control memory access is as follows: an agent can request a read or write at any time. The control memory will continue in its current mode (read or write) until no requests of that type are pending. Then, it will switch and service requests of the other mode. The CPU has the highest priority if the memory controller is handling accesses of the mode that the CPU requests. Other agents are granted access on a first-come first-served basis if the memory controller is handling accesses of the mode the agent requests. Agent TX_SAR RX_SAR UTOPIA (LUT) CPU Access types Reads and writes Reads and writes Reads and writes Reads and writes
Table 36 - Types of Control Memory Accesses For Each Agent
5.4
Register Overview
This section describes the MT90503's internal registers. An 8 KB memory block is reserved for the register mapping. The register descriptions are grouped in the following sections: * * * * * * * * * CPU Module Interface Main Registers UTOPIA Module TDM Module TX_SAR Module RX_SAR Module Clock Registers Miscellaneous Registers H.100/H.110 Bus Registers
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5.5 5.5.1 Detailed Register Description CPU Registers
Data Sheet
Address: 100h Label: control Reset Value: 0000h Label
nreset_registers
Bit Position
0
Type
RW
Description
Controls the reset for the MAINREG module and certain CPU functions. '1' out of reset. '0' in reset. Should not be removed unless mclk is present. Resets all other parts of the chip. '1' out of reset. '0' in reset. Should not be removed unless mclk is present. nreset for UTOPIA TXA clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. nreset for UTOPIA TXB clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. nreset for UTOPIA TXC clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. nreset for UTOPIA RXA clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. nreset for UTOPIA RXB clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. nreset for UTOPIA RXC clock (syncronized on mclk_src). This reset should not be removed unless the corresponding clock is present. For future use: reserved for mem_clk oe (TTL) For future use: reserved for PECL oe Enables the mem_clk TTL output to toggle, active high Enables the mem_clk PECL output to toggle, active high '0' = mem_clk_i pin, '1' = mem_clk PECL pins When '0', only 1 access can be treated at a time. When '1', write cache contains 128 accesses. If this bit is '1', the average latency to perform a write will be reduced, but the worst-case latency will be increased. Reserved. Must be set t o "0". When '1', all the status bits in the register will be set.
nreset_chip_mclk_src nreset_txa_clk_mclk_src
1 2
RW RW
nreset_txb_clk_mclk_src
3
RW
nreset_txc_clk_mclk_src
4
RW
nreset_rxa_clk_mclk_src
5
RW
nreset_rxb_clk_mclk_src
6
RW
nreset_rxc_clk_mclk_src
7
RW
reserved reserved mem_clk_o_enable mem_clk_pecl_enable mem_clk_input_sel write_cache_enable
8 9 10 11 12 13
RW RW RW RW RW RW
reserved test_status
14 15
RW TS
Table 37 - CPU Control Register
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Address: 102h Label: status0 Reset Value: 0000h Label reserved reserved reserved internal_read_timeout inmo_read_done reserved Bit Position 0 1 2 3 4 15:5 Type RO RO RO ROL ROL ROL Description Reserved. Always read as "0". Reserved. Always read as "0". Reserved. Always read as "0".
Data Sheet
Goes high if a read access has been active for 32k mclk_src cycles without completion. Fatal chip error. Indicates that an extended indirect access has completed. This is used to indicate to the host that read data is ready. Reserved. Always read as "0000_0000_000"
Table 38 - CPU Status Register
Address: 104h Label: status0_ie Reset Value: 0000h Label reserved reserved reserved internal_read_timeout_ie inmo_read_done_ie reserved Bit Position 0 1 2 3 4 15:5 Type RO RO RO IE IE RO Description Reserved. Always read as "0". Reserved. Always read as "0". Reserved. Always read as "0". When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as "0000_0000_000".
Table 39 - CPU Interrupt Enable Register
Address: 10EH Label: counters Reset Value: 0000h Label emul_mode Bit Position 1:0 Type EMO Description Indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. These bits are only present for tests and should never be used. Reserved. Must be "0000_0000_0000_00"
reserved
15:2
RW
Table 40 - CPU Counter Register
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Address: 120h Label: led1 Reset Value: 3FD0h Label mclk_src_freq[6:0] led_flash_freq[8:0] Bit Position 6:0 15:7 Type RW RW Description mclk_src Frequency in MHz
Data Sheet
Determines the time in ms that the LEDs will be turned off to indicate link activity.
Table 41 - LED1 Register
Address: 122h Label: led2 Reset Value: 0000h Label led_test_mode reserved Bit Position 0 15:1 Type RW RW Description If '0', the LED Flashing time will be determined in ms. If '1', the LED Flashing time will be determined in us. Reserved. Must be "0000_0000_0000_000"
Table 42 - LED2 Register
Address: 128h Label: pll_conf Reset Value: 00A1h Label pll_div_x Bit Position 2:0 Type RW Description Divides mclk_src before entering the REF pin of the fast_clk PLL. Together, pll_div_x and pll_div_y determine the speed of fast_clk, which must be between 160 and 200 MHz. Divides the feedback path from the output pin of the fast_clk PLL. Together, pll_div_x and pll_div_y determine the speed of fast_clk, which must be between 160 and 200 MHz. Divides fast_clk to generate mem_clk If '1', mclk_src divided by pll_div_x becomes fast_clk, bypassing the fast_clk PLL Resets the module that divides mclk_src before being used as the REF pin of the fast_clk PLL Reserved. Always read as "000"
pll_div_y
5:3
RW
pll_div_z pll_bypass nreset_pll_async reserved
10:6 11 12 15:13
RW RW RW RO
Table 43 - PLL Configuration Register
106
Zarlink Semiconductor Inc.
MT90503
Address: 130h Label: inmo_a_gpi0 Reset Value: 0000h Label inmo_a_in[14:0] reserved Bit Position 14:0 15 Type RO RO Description Current level of the corresponding pin Reserved. Always read as "0"
Data Sheet
Table 44 - Intel/Motorola Address Register
Address: 132h Label: inmo_a_gpi1 Reset Value: 0000h Label inmo_a_rise0 inmo_a_rise1 inmo_a_rise2 inmo_a_rise3 inmo_a_rise4 inmo_a_rise5 inmo_a_rise6 inmo_a_rise7 inmo_a_rise8 inmo_a_rise9 inmo_a_rise10 inmo_a_rise11 inmo_a_rise12 inmo_a_rise13 inmo_a_rise14 reserved Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL RO Description This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' Reserved. Always read as "0:"
Table 45 - Intel/Motorola Address Rise Register
107
Zarlink Semiconductor Inc.
MT90503
Address: 136h Label: inmo_a_gpi2 Reset Value: 0000h Label inmo_a_fall0 inmo_a_fall1 inmo_a_fall2 inmo_a_fall3 inmo_a_fall4 inmo_a_fall5 inmo_a_fall6 inmo_a_fall7 inmo_a_fall8 inmo_a_fall9 inmo_a_fall10 inmo_a_fall11 inmo_a_fall12 inmo_a_fall13 inmo_a_fall14 reserved Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL RO Description
Data Sheet
This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' Reserved. Always read as "0"
Table 46 - Intel/Motorla Address Fall Register
Address: 140h Label: inmo_d_gpo Reset Value: 0000h Label inmo_d_out8 inmo_d_out9 inmo_d_out10 inmo_d_out11 Bit Position 0 1 2 3 Type RW RW RW RW Description This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit
Table 47 - Intel/Motorola Data Out Register
108
Zarlink Semiconductor Inc.
MT90503
Address: 140h Label: inmo_d_gpo Reset Value: 0000h Label inmo_d_out12 inmo_d_out13 inmo_d_out14 inmo_d_out15 inmo_d_oe8 inmo_d_oe9 inmo_d_oe10 inmo_d_oe11 inmo_d_oe12 inmo_d_oe13 inmo_d_oe14 inmo_d_oe15 Bit Position 4 5 6 7 8 9 10 11 12 13 14 15 Type RW RW RW RW RW RW RW RW RW RW RW RW Description
Data Sheet
This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin. This is OE bit used to drive the corresponding pin.
Table 47 - Intel/Motorola Data Out Register (continued)
Address 142h: Label: inmo_d_gpi0 Reset Value: 0000h Label inmo_d_in8 inmo_d_in9 inmo_d_in10 inmo_d_in11 inmo_d_in12 inmo_d_in13 inmo_d_in14 inmo_d_in15 reserved Bit Position 0 1 2 3 4 5 6 7 15:8 Type RO RO RO RO RO RO RO RO RO Description Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Current level of the corresponding pin Reserved. Always read as "0000_0000"
Table 48 - Intel/Motorola Data In Register
109
Zarlink Semiconductor Inc.
MT90503
Address 144h: Label: inmo_d_gpi1 Reset Value: 0000h Label inmo_d_rise8 inmo_d_rise9 inmo_d_rise10 inmo_d_rise11 inmo_d_rise12 inmo_d_rise13 inmo_d_rise14 inmo_d_rise15 inmo_d_fall8 inmo_d_fall9 inmo_d_fall10 inmo_d_fall11 inmo_d_fall12 inmo_d_fall13 inmo_d_fall14 inmo_d_fall15 Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description
Data Sheet
This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '0' to '1' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0' This bit is set if the corresponding pin goes for '1' to '0'
Table 49 - Intel/Motorola Data Rise/Fall Register
5.5.2
Main Registers
Address: 200h Label: control Reset Value: 0000h Label reserved test_status Bit Position 14:0 15 Type RO TS Description Reserved. Always read as "0000_0000_0000_000" When '1', all the status bits in the register will be set.
Table 50 - Main Control Register
110
Zarlink Semiconductor Inc.
MT90503
Address: 202h Label: status0 Reset Value: 0000h Label cmem_parity_error0 Bit Position 0 Type ROL Description
Data Sheet
Indicates a parity error on data received from the control memory on the data bits [7:0]. This will only be detected if cmem_parity_conf[0] is '0'. Indicates a parity error on data received from the control memory on the data bits [15:8]. This will only be detected if cmem_parity_conf[1] is '0'. Indicates a parity error on data received from the data memory on the data bits [7:0]. This will only be detected if dmem_parity_conf[0] is '0'. Indicates a parity error on data received from the data memory on the data bits [15:8]. This will only be detected if dmem_parity_conf[1] is '0'. Reserved. Must be "0000_0000_0000"
cmem_parity_error1
1
ROL
dmem_parity_error0
2
ROL
dmem_parity_error1
3
ROL
reserved
15:4
RW
Table 51 - Main Status Register
Address: 204h Label: status0_ie Reset Value: 0000h Label cmem_parity_error0_ie cmem_parity_error1_ie dmem_parity_error0_ie dmem_parity_error1_ie reserved Bit Position 0 1 2 3 15:4 Type IE IE IE IE RW Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Must be "0000_0000_0000"
Table 52 - Main Interrupt Enable Register
111
Zarlink Semiconductor Inc.
MT90503
Address: counters Label: 20Eh Reset Value: 0000h Label emul_mode Bit Position 1:0 Type EMO Description
Data Sheet
Indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. These bits are only present for tests and should never be used. Reserved. Must be "0000_0000_0000_00"
reserved
15:2
RW
Table 53 - Main Counter Register
Address: 220h Label: interrupt_flags Reset Value: 0000h Label cpureg_interrupt_active mainreg_interrupt_active utoreg_interrupt_active txreg_interrupt_active rxreg_interrupt_active miscreg_interrupt_active wheelreg_interrupt_active clkreg_interrupt_active tdmreg_interrupt_active mastreg_interrupt_active Bit Position 0 1 2 3 4 5 6 7 8 9 Type RO RO RO RO RO RO RO RO RO RO Description When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active. When '1', indicates that the interrupt request for this module is active.
Table 54 - Interrupt Flags Register
112
Zarlink Semiconductor Inc.
MT90503
Address: 220h Label: interrupt_flags Reset Value: 0000h Label casalarm_interrupt_active Bit Position 10 Type RO Description
Data Sheet
The CAS alarm occurs after the CAS alarm timeout period or if the CAS buffer becomes half full. This is used to ensure that the host can empty the CAS change buffer in a timely manner without having to poll its fill continuously. When '0', the clock divisor module is held in reset. The clock recovery alarm occurs after the clock recovery alarm timeout period or if either clock recovery buffer becomes half full. This is used to ensure that the host can empty the clock recovery point buffers in a timely manner without having to poll its fill continuously. The AAL0 alarm occurs after the AAL0 alarm timeout period or if the AAL0 buffer becomes half full. This is used to ensure that the host can empty the AAL0 cell buffer in a timely manner without having to poll its fill continuously. The error alarm occurs after the error alarm timeout period or if the error report structure buffer becomes half full. This is used to ensure that the host can empty the error structure buffer in a timely manner without having to poll its fill continuously. Software must write this bit to '1', when it has finished servicing interrupts.
tdmalarm_interrupt_active clkrecovalarm_interrupt_active
11 12
RO RO
aal0alarm_interrupt_active
13
RO
erroralarm_interrupt_active
14
RO
interrupt1_treated
15
PUL
Table 54 - Interrupt Flags Register (continued)
Address: 224h Label: interrupt1_conf Reset Value: 0000h Label min_interrupt1_period Bit Position 13:0 Type RW Description Number of us between interrupts (minimum). When 0000h, these is no minimum interval between interrupts. Programming this prevents the host from being flooded with interrupts. Each interrupt will last 1 us. Interrupt polarity and output enable. "00"=active low (open-collector); "01"=active high (open-collector); "10" = drive low; "11" = drive high. Drive low or drive high means that the pin's value will not change regardless of internal interrupts.
interrupt1_polarity
15:14
RW
Table 55 - Interrupt1 Configuration Register
113
Zarlink Semiconductor Inc.
MT90503
Data Sheet
Address: 226h Label: interrupt2_conf Reset Value: 0000h Label reserved interrupt2_polarity Bit Position 13:0 15:14 Type RW RW Description Reserved. Must be "0000_0000_0000_00" Interrupt polarity and output enable. "00"=active low (open-collector); "01"=active high (open-collector); "10" = drive low; "11" = drive high. Drive low or drive high means that the pin's value will not change regardless of internal interrupts.
Table 56 - Interrupt2 Configuration Register
Address: 228h Label: interrupt1_enable Reset Value: 0000h Label cpureg_interrupt1_enable mainreg_interrupt1_enable utoreg_interrupt1_enable txreg_interrupt1_enable rxreg_interrupt1_enable miscreg_interrupt1_enable wheelreg_interrupt1_enable clkreg_interrupt1_enable tdmreg_interrupt1_enable mastreg_interrupt1_enable Bit Position 0 1 2 3 4 5 6 7 8 9 Type RW RW RW RW RW RW RW RW RW RW Description When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0].
Table 57 - Interrupt1 Enable Register
114
Zarlink Semiconductor Inc.
MT90503
Address: 228h Label: interrupt1_enable Reset Value: 0000h Label casalarm_interrupt1_enable tdmalarm_interrupt1_enable clkrecovalarm_interrupt1_enable aal0alarm_interrupt1_enable erroralarm_interrupt1_enable reserved Bit Position 10 11 12 13 14 15 Type RW RW RW RW RW RW Description
Data Sheet
When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. Reserved. Must always be "0"
Table 57 - Interrupt1 Enable Register (continued)
Address: 22Ch Label: interrupt2_enable Reset Value: 0000h Label cpureg_interrupt2_enable mainreg_interrupt2_enable utoreg_interrupt2_enable txreg_interrupt2_enable rxreg_interrupt2_enable miscreg_interrupt2_enable wheelreg_interrupt2_enable clkreg_interrupt2_enable Bit Position 0 1 2 3 4 5 6 7 Type RW RW RW RW RW RW RW RW Description When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1].
Table 58 - Interrupt2 Enable Register
115
Zarlink Semiconductor Inc.
MT90503
Address: 22Ch Label: interrupt2_enable Reset Value: 0000h Label tdmreg_interrupt2_enable mastreg_interrupt2_enable casalarm_interrupt2_enable tdmalarm_interrupt2_enable clkrecovalarm_interrupt2_ena ble aal0alarm_interrupt2_enable erroralarm_interrupt2_enable reserved Bit Position 8 9 10 11 12 13 14 15 Type RW RW RW RW RW RW RW RW Description
Data Sheet
When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. Reserved. Must always be "0"
Table 58 - Interrupt2 Enable Register (continued)
Address: 230h Label: utopia_clock1 Reset Value: 0000h Label utopia_porta_clk_oe Bit Position 0 Type RW Description 0'=tri-state the txa_clk and rxa_clk; '1'=drive the txa_clk and rxa_clk. This should only be enabled if the chip is to drive these clocks, and only after the clock generation has been correctly programmed. 0'=tri-state the txb_clk and rxb_clk; '1'=drive the txb_clk and rxb_clk. This should only be enabled if the chip is to drive these clocks, and only after the clock generation has been correctly programmed. This bit must be '0' as UTOPIA port C clocks must be input only.
utopia_portb_clk_oe
1
RW
utopia_portc_clk_oe
2
RW
Table 59 - Utopia Clock Register
116
Zarlink Semiconductor Inc.
MT90503
Address: 230h Label: utopia_clock1 Reset Value: 0000h Label utopia_txa_clk_select[1:0] Bit Position 4:3 Type RW Description
Data Sheet
"00" = select clock divisor A; "01" = select clock divisor B; "10" = select clock divisor C; "11" = reserved. There are 3 integer clock divisors used to generate the UTOPIA clocks, and each of the 6 UTOPIA clocks can be selected as any one of the 3. "00" = select clock divisor A; "01" = select clock divisor B; "10" = select clock divisor C; "11" = reserved. There are 3 integer clock divisors used to generate the UTOPIA clocks, and each of the 6 UTOPIA clocks can be selected as any one of the 3. Reserved. "00" = select clock divisor A; "01" = select clock divisor B; "10" = select clock divisor C; "11" = reserved. "00" = select clock divisor A; "01" = select clock divisor B; "10" = select clock divisor C; "11" = reserved. Reserved. Reserved. Must always be "0"
utopia_txb_clk_select[1:0]
6:5
RW
utopia_txc_clk_select[1:0] utopia_rxa_clk_select[1:0]
8:7 10:9
RW RW
utopia_rxb_clk_select[1:0]
12:11
RW
utopia_rxc_clk_select[1:0] reserved
14:13 15
RW RW
Table 59 - Utopia Clock Register (continued)
Address: 232h Label: utopia_gena Reset Value: 0001h Label utopia_clk_diva[5:0] utopia_clk_divisor_load_nowa utopia_clk_inva utopia_clk_srca[2:0] Bit Position 5:0 6 7 10:8 Type RW PUL RW RW Description Integer divisor for input UTOPIA clock. Divides the selected clock source. Written to '1' when the source, divisor and inv. have been correctly programmed. Inverts the output of the clock divisor "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. When '0', the clock divisor module is held in reset.
utopia_clk_divisor_reseta
11
RW
Table 60 - Utopia Clock Generation A Register
117
Zarlink Semiconductor Inc.
MT90503
Address: 232h Label: utopia_gena Reset Value: 0001h Label reserved Bit Position 15:12 Type RW Description Reserved. Must always be "0000"
Data Sheet
Table 60 - Utopia Clock Generation A Register
Address: 234h Label: utopia_genb Reset Value: 0001h Label utopia_clk_divb[5:0] utopia_clk_divisor_load_nowb utopia_clk_invb utopia_clk_srcb[2:0] Bit Position 5:0 6 7 10:8 Type RW PUL RW RW Description Integer divisor for input UTOPIA clock. Divides the selected clock source. Written to '1' when the source, divisor and inv. have been correctly programmed. Inverts the output of the clock divisor "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. When '0', the clock divisor module is held in reset. Reserved. Must always be "0000"
utopia_clk_divisor_resetb reserved
11 15:12
RW RW
Table 61 - Utopia Clock Generation B Register
Address: 236h Label: utopia_genc Reset Value: 0001h Label utopia_clk_divc[5:0] utopia_clk_divisor_load_nowc utopia_clk_invc utopia_clk_srcc[2:0] Bit Position 5:0 6 7 10:8 Type RW PUL RW RW Description Integer divisor for input UTOPIA clock. Divides the selected clock source. Written to '1' when the source, divisor and inv. have been correctly programmed. Inverts the output of the clock divisor "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk.
Table 62 - Utopia Clock Generation C Register
118
Zarlink Semiconductor Inc.
MT90503
Address: 236h Label: utopia_genc Reset Value: 0001h Label utopia_clk_divisor_resetc reserved Bit Position 11 15:12 Type RW RW Description
Data Sheet
When '0', the clock divisor module is held in reset. Reserved. Must always be "0000"
Table 62 - Utopia Clock Generation C Register
Address: 240h Label: cmem_parity0 Reset Value: 0000h Label cmem_parity_conf[1:0] Bit Position 1:0 Type RW Description 0' = parity bits; '1' = user data. In normal chip operation, this field should be set to "00", because the chip does not use the parity bits of the control memory. Mask of address bits [18:16] to be used to generate parity for the control memory. A '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. Reserved. Must always be "0000" Mask of data bits to be used to generate parity for the control memory. A '1' in one of these bits indicates that the data bit will be used to generate parity.
cmem_parity_generation_add_mask [18:16]
4:2
RW
reserved cmem_parity_generation_data_mask
7:5 15:8
RO RW
Table 63 - Control Memory Parity0 Register
Address: 242h Label: cmem_parity1 Reset Value: 0000h Label cmem_parity_generation_add_mask [15:0] Bit Position 15:0 Type RW Description Mask of address bits [15:0] to be used to generate parity for the control memory. A '1' in one of these bits indicates that the corresponding address bit will be used to generate parity.
Table 64 - Control Memory Parity1 Register
119
Zarlink Semiconductor Inc.
MT90503
Address: 244h Label: cmem_conf Reset Value: 0010h Label cmem_add_lines cmem_mem_type cmem_rw_ta reserved Bit Position 1:0 3:2 4 15:5 Type RW RW RW RO Description
Data Sheet
"11" = 1 MB per chip; "10" = 512 KB per chip; "01" = 256KB per chip; "00" = 128 KB per chip "00" = flowthrough ZBT; "01" = flowthrough SSRAM; "10" = pipelined ZBT; "11" = pipelined SSRAM. 0 = no read/write turn-around cycles; 1 = 1 read/write turn-around cycle. Reserved. Always read as "0000_0000_000"
Table 65 - Control Memory Configuration Register
Address: 248h Label: dmem_parity0 Reset Value: 0000h Label dmem_parity_conf[1:0] dmem_parity_generation_add_mask [20:16] Bit Position 1:0 6:2 Type RW RW Description 0' = parity bits; '1' = user data. Mask of address bits [20:16] to be used to generate parity for the data memory. A '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. Reserved. Always read as "0" Mask of data bits to be used to generate parity for the data memory. A '1' in one of these bits indicates that the corresponding data bit will be used to generate parity.
reserved dmem_parity_generation_data_mask
7 15:8
RO RW
Table 66 - Data Memory Parity 0 Register
120
Zarlink Semiconductor Inc.
MT90503
Address: 24Ah Label: dmem_parity1 Reset Value: 0000h Label dmem_parity_generation_add_mask [15:0] Bit Position 15:0 Type RW Description
Data Sheet
Mask of address bits [15:0] to be used to generate parity for the data memory. A '1' in one of these bits indicates that the corresponding address bit will be used to generate parity.
Table 67 - Data Memory Parity 1 Register
Address: 24Ch Label: dmem_conf Reset Value: 0010h Label dmem_add_lines dmem_mem_type dmem_rw_ta reserved Bit Position 1:0 3:2 4 15:5 Type RW RW RW RO Description "11" = 1 MB per chip; "10" = 512 KB per chip; "01" = 256KB per chip; "00" = 128 KB per chip "00" = flowthrough ZBT; "01" = flowthrough SSRAM; "10" = pipelined ZBT; "11" = pipelined SSRAM. 0 = no read/write turn-around cycles; 1 = 1 read/write turn-around cycle. Reserved. Always read as "0000_0000_000"
Table 68 - Data Memory Configuration Register
5.5.3
UTOPIA Registers
Address: 300h Label: control Reset Value: 0900h Label rxa_ena rxa_sar rxa_width rxb_ena rxb_sar rxb_width Bit Position 0 1 2 3 4 5 Type RW RW RW RW RW RW Enables UTOPIA port RXA 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus Enables UTOPIA port RXB 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus Table 69 - Utopia Control Register Description
121
Zarlink Semiconductor Inc.
MT90503
Address: 300h Label: control Reset Value: 0900h Label txa_sar txa_width txa_multiphy txb_sar txb_width txb_multiphy add_pin_ena reserved null_cell_elim test_status Bit Position 6 7 8 9 10 11 12 13 14 15 Type RW RW RW RW RW RW RW RW RW TS Description 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus
Data Sheet
0' = always drive DAT/PAR/SOC pins; '1' = only drive when selected. Only applicable when chip is in PHY mode. 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus 0' = always drive DAT/PAR/SOC pins; '1' = only drive when selected. Only applicable when chip is in PHY mode. If '1', UTOPIA port A is level-2 with addressing. When this bit is set, rxb_width and txb_width must be '0'. Reserved. Must always be "0" When '1', all cells with VPI and VCI equal to '0' will be discarded. Otherwise, they will be kept and treated normally. When '1', all the status bits in the register will be set.
Table 69 - Utopia Control Register (continued)
Address: 302h Label: control1 Reset Value: 0008h Label rxc_ena rxc_sar txc_sar txc_multiphy uto_output_enable Bit Position 0 1 2 3 4 Type RW RW RW RW RW Description Enables UTOPIA port RXC 0' = chip acts as PHY, '1' = chip acts as SAR 0' = chip acts as PHY, '1' = chip acts as SAR 0' = always drive DAT/PAR/SOC pins; '1' = only drive when selected. Only applicable when chip is in PHY mode. 0' Tri-states the ENA or CLAV pin driven by the chip. '1' drives. This bit should be set to '1' after all PHY/SAR register bits have been programmed, but before all rx_ena bits are set. "00" = PHY alarm disabled, "01" = PHY alarm active-high, "10" = PHY alarm active-low, "11" = reserved.
phy_alarm_pol
6:5
RW
Table 70 - Utopia Control1 Register
122
Zarlink Semiconductor Inc.
MT90503
Address: 302h Label: control1 Reset Value: 0008h Label long_lut_entries Bit Position 7 Type RW Description
Data Sheet
When '0', LUT entries are 4 bytes long. When '1', LUT entries are 8 bytes long. Long LUT entries should only be used if header translation is to be performed. 1' consider NNI VPI bits for null cell elimination for port RXA. If '0', the high 4 bits of the header (GFC field) will be ignored for null cell elimination. 1' consider NNI VPI bits for null cell elimination for port RXB. If '0', the high 4 bits of the header (GFC field) will be ignored for null cell elimination. 1' consider NNI VPI bits for null cell elimination for port RXC. If '0', the high 4 bits of the header (GFC field) will be ignored for null cell elimination. When '0', phya_tx_led pin functions as a LED. When '1', functions as GPIO. When '0', phya_rx_led pin functions as a LED. When '1', functions as GPIO. When '0', phyb_tx_led pin functions as a LED. When '1', functions as GPIO. When '0', phyb_rx_led pin functions as a LED. When '1', functions as GPIO. Reserved. Must always be "0"
rxa_nni_null_elim
8
RW
rxb_nni_null_elim
9
RW
rxc_nni_null_elim
10
RW
phya_tx_led_conf phya_rx_led_conf phyb_tx_led_conf phyb_rx_led_conf reserved
11 12 13 14 15
RW RW RW RW RW
Table 70 - Utopia Control1 Register (continued)
Address: 304h Label: status0 Reset Value: 0000h Label rx_cell_loss outa_cell_loss outb_cell_loss outc_cell_loss cell_loss_rollover Bit Position 0 1 2 3 4 Type ROL ROL ROL ROL CRL Description Indicates an overflow in the buffer from UTOPIA to the RX SAR Indicates an overflow in the output buffer for port TXA Indicates an overflow in the output buffer for port TXB Indicates an overflow in the output buffer for port TXC Indicates that the cell_loss_counter register has wrapped
Table 71 - Utopia Status 0 Register
123
Zarlink Semiconductor Inc.
MT90503
Address: 304h Label: status0 Reset Value: 0000h Label tx_arr_rollover rx_dep_rollover ia_arr_rollover oa_dep_rollover ib_arr_rollover ob_dep_rollover ic_arr_rollover oc_dep_rollover rxa_parity_error rxb_parity_error rxc_parity_error Bit Position 5 6 7 8 9 10 11 12 13 14 15 Type CRL CRL CRL CRL CRL CRL CRL CRL ROL ROL ROL Description
Data Sheet
Indicates that the tx_sar_cell_arrival register has wrapped Indicates that the rx_sar_cell_departure register has wrapped Indicates that the porta_cell_arrival register has wrapped Indicates that the porta_cell_departure register has wrapped Indicates that the portb_cell_arrival register has wrapped Indicates that the portb_cell_departure register has wrapped Indicates that the portc_cell_arrival register has wrapped Indicates that the portc_cell_departure register has wrapped Indicates a parity error on port RXA Indicates a parity error on port RXB Indicates a parity error on port RXC
Table 71 - Utopia Status 0 Register (continued)
Address: 30Ch Label: status2 Reset Value: 0000h Label phy_alarma phy_alarmb test_a_bit test_b_bit reserved Bit Position 0 1 2 3 15:4 Type ROLO ROLO ROL ROL RW Description This bit is set when phya_alm pin is active. Active polarity is determined by phy_alarm_pol register This bit is set when phyb_alm pin is active. Active polarity is determined by phy_alarm_pol register Bit is set when look-up engine gives a pulse on clock recovery VC A. Used for tests. Bit is set when look-up engine gives a pulse on clock recovery VC B. Used for tests. Reserved. Must always be "0000_0000_0000"
Table 72 - Utopia Status 2 Register
Address: 30Eh Label: status2_ie Reset Value: 0000h Table 73 - Utopia Interrupt Enable 2 Register
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Zarlink Semiconductor Inc.
MT90503
Label phy_alarma_ie phy_alarmb_ie test_a_bit_ie test_b_bit_ie reserved Bit Position 0 1 2 3 15:4 Type IE IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 73 - Utopia Interrupt Enable 2 Register Address: 310h Label: counters Reset Value: 0000h Label emul_mode Bit Position 1:0 Type EMO Description Indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. These bits are only present for tests and should never be used. When emul_mode = "11", writing '1' to this bit will increment the cell_loss counter by 1 When emul_mode = "11", writing '1' to this bit will increment the tx_arr counter by 1 When emul_mode = "11", writing '1' to this bit will increment the rx_dep counter by 1 When emul_mode = "11", writing '1' to this bit will increment the ia_arr counter by 1 When emul_mode = "11", writing '1' to this bit will increment the oa_dep counter by 1 When emul_mode = "11", writing '1' to this bit will increment the ib_arr counter by 1 When emul_mode = "11", writing '1' to this bit will increment the ob_dep counter by 1 When emul_mode = "11", writing '1' to this bit will increment the ic_arr counter by 1 When emul_mode = "11", writing '1' to this bit will increment the oc_dep counter by 1 Reserved. Must always be "0000_0"
cell_loss_emul tx_arr_emul rx_dep_emul ia_arr_emul oa_dep_emul ib_arr_emul ob_dep_emul ic_arr_emul oc_dep_emul reserved
2 3 4 5 6 7 8 9 10 15:11
EMU EMU EMU EMU EMU EMU EMU EMU EMU RW
Table 74 - Utopia Counters Register
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Zarlink Semiconductor Inc.
MT90503
Data Sheet
Address: 312h Label: cell_loss_counters Reset Value: 0000h Label cell_loss Bit Position 15:0 Type CNT Description Counts the number of cells lost due to fifo overflows. This includes the output fifos from the look-up engine to the: RX SAR, ports TXA, TXB, TXC.
Table 75 - Cell Loss Counters Register
Address: 320h Label: porta_look_up_base Reset Value: 0000h Label luta_base Bit Position 15:0 Type RW Description Bits 19:4 of the address of the look-up table for port A.
Table 76 - Port A Look Up Table Address Register
Address: 322h Label: porta_num_vpi_vci_bits Reset Value: 0000h Label num_vpi_vci_bits Bit Position 15:0 Type RW Description Indicates the total number of bits that are used to decode the look-up address for port A. 0001h = 1 bit used, FFFFh = 16 bits used. When subtracted from vci_n, this indicates the number of VPI bits used.
Table 77 - Port A VPI/VCI Identification Register
Address: 324h Label: porta_concatenation Reset Value: 0000h Label vci_na Bit Position 4:0 Type RW Description Indicates the number of VCI bits used to decode the look-up address for port A.
Table 78 - Port A Concatenation Register
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Zarlink Semiconductor Inc.
MT90503
Address: 324h Label: porta_concatenation Reset Value: 0000h Label reserved Bit Position 15:5 Type RW Description Reserved. Must always be "0000_0000_000"
Data Sheet
Table 78 - Port A Concatenation Register
Address: 328h Label: porta_vpi_match Reset Value: 0000h Label vpi_matcha Bit Position 11:0 Type RW Description For a cell from port A to be considered valid, any bits in its VPI whose corresponding bits in reg 32Ah are '1' must have the value contained in this register. Reserved. Must always be "0000"
reserved
15:12
RW
Table 79 - Port A VPI Match Register Address: 32Ah Label: porta_vci_mask Reset Value: 0000h Label vpi_maska Bit Position 11:0 Type RW Description For a cell from port A to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 328h. Reserved. Must always be "0000"
reserved
15:12
RW
Table 80 - Port A VCI Mask Register
Address: 32Ch Label: porta_vci_match Reset Value: 0000h Label vci_matcha Bit Position 15:0 Type RW Description For a cell from port A to be considered valid, any bits in its VCI whose corresponding bits in reg 32Eh are '1' must have the value contained in this register.
Table 81 - Port A VCI Match Register
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Zarlink Semiconductor Inc.
MT90503
Address: 32Eh Label: porta_vci_mask Reset Value: 0000h Label vci_maska Bit Position 15:0 Type RW Description
Data Sheet
For a cell from port A to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 32Ch.
Table 82 - Port A VCI Mask Register
Address: 330h Label: porta_cell_arrival_high Reset Value: 0000h Label ia_arr[31:16] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells received on port A.
Table 83 - Port A Cell Arrival Counter High Register Address: 332h Label: porta_cell_arrival_low Reset Value: 0000h Label ia_arr[15:0] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells received on port A.
Table 84 - Port A Cell Arrival Counter Low Register
Address: 334h Label: porta_cell_departure_high Reset Value: 0000h Label oa_dep[31:16] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells transmitted on port A.
Table 85 - Port A Cell Departure Counter High Register
128
Zarlink Semiconductor Inc.
MT90503
Address: 336h Label: porta_cell_departure_low Reset Value: 0000h Label oa_dep[15:0] Bit Position 15:0 Type CNT Description
Data Sheet
Freerunning counter of the number of cells transmitted on port A.
Table 86 - Port A Cell Departure Low Register
Address: 338h Label: porta_overflow0 Reset Value: 0000h Label ia_rx_cell_max Bit Position 4:0 Type RW Description If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port A output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port B output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0"
ia_oa_cell_max
9:5
RW
ia_ob_cell_max
14:10
RW
reserved
15
RW
Table 87 - Port A Overflow0 Register
Address: 33Ah Label: porta_overflow1 Reset Value: 0000h Label ia_oc_cell_max Bit Position 4:0 Type RW Description If the cell fill of the Port C output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0000_0000_000"
reserved
15:5
RW
Table 88 - Port A Overflow1 Register
129
Zarlink Semiconductor Inc.
MT90503
Address: 33Ch Label: porta_address Reset Value: 0000h Label porta_add reserved Bit Position 4:0 15:5 Type RW RW Description
Data Sheet
UTOPIA address to which the chip will repond when programmed as a level-2 PHY. Reserved. Must always be "0000_0000_000"
Table 89 - Port A Address Register
Address: 340h Label: portb_look_up_b Reset Value: 0000h Label lutb_base Bit Position 15:0 Type RW Description Bits 19:4 of the address of the look-up table for port B.
Table 90 - Port B Look Up Table Register Address: 342h Label: portb_num_vpi_vci_bits Reset Value: 0000h Label num_vpi_vci_bits Bit Position 15:0 Type RW Description Indicates the total number of bits that are used to decode the look-up address for port B. 0001h = 1 bit used, FFFFh = 16 bits used. When subtracted from vci_n, this indicates the number of VPI bits used.
Table 91 - Port B VPI/VCI Identification Register
Address: 344h Label: portb_concatenation Reset Value: 0000h Label vci_nb reserved Bit Position 4:0 15:5 Type RW RW Description Indicates the number of VCI bits used to decode the look-up address for port B. Reserved. Must always be "0000_0000_000"
Table 92 - Port B Concatenation Register
130
Zarlink Semiconductor Inc.
MT90503
Address: 348h Label: portb_vpi_match Reset Value: 0000h Label vpi_matchb Bit Position 11:0 Type RW Description
Data Sheet
For a cell from port B to be considered valid, any bits in its VPI whose corresponding bits in reg 34Ah are '1' must have the value contained in this register. Reserved. Must always be "0000"
reserved
15:12
RW
Table 93 - Port B VPI Match Register
Address: 34Ah Label: portb_vpi_mask Reset Value: 0000h Label vpi_maskb Bit Position 11:0 Type RW Description For a cell from port B to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 348h. Reserved. Must always be "0000"
reserved
15:12
RW
Table 94 - Port B VPI Mask Register
Address: 34Ch Label: portb_vci_match Reset Value: 0000h Label vci_matchb Bit Position 15:0 Type RW Description For a cell from port B to be considered valid, any bits in its VCI whose corresponding bits in reg 34Eh are '1' must have the value contained in this register.
Table 95 - Port B VCI Match Register
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Zarlink Semiconductor Inc.
MT90503
Address: 34Eh Label: portb_vci_mask Reset Value: 0000h Label vci_maskb Bit Position 15:0 Type RW Description
Data Sheet
For a cell from port B to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 34Ch.
Table 96 - Port B VCI Mask Register
Address: 350h Label: portb_cell_arrival_high Reset Value: 0000h Label ib_arr[31:16] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells received on port B.
Table 97 - Port B Cell Arrival Counter High Register
Address: 352h Label: portb_cell_arrival_low Reset Value: 0000h Label ib_arr[15:0] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells received on port B.
Table 98 - Port B Cell Arrival Counter Low Register
Address: 354h Label: portb_cell_departure_high Reset Value: 0000h Label ob_dep[31:16] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells transmitted on port B.
Table 99 - Port B Cell Departure Counter High Register
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Zarlink Semiconductor Inc.
MT90503
Address: 356h Label: portb_cell_departure_low Reset Value: 0000h Label ob_dep[15:0] Bit Position 15:0 Type CNT Description
Data Sheet
Freerunning counter of the number of cells transmitted on port B.
Table 100 - Port B Cell Departure Counter Low Register
Address: 358h Label: portb_overflow0 Reset Value: 0000h Label ib_rx_cell_max Bit Position 4:0 Type RW Description If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port A output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port B output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0"
ib_oa_cell_max
9:5
RW
ib_ob_cell_max
14:10
RW
reserved
15
RW
Table 101 - Port B Overflow0 Register
Address: 35Ah Label: portb_overflow1 Reset Value: 0000h Label ib_oc_cell_max Bit Position 4:0 Type RW Description If the cell fill of the Port C output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0000_0000_000"
reserved
15:5
RW
Table 102 - Port B Overflow1 Register
133
Zarlink Semiconductor Inc.
MT90503
Address: 360h Label: portc_look_up_base Reset Value: 0000h Label lutc_base Bit Position 15:0 Type RW Description
Data Sheet
Bits 19:4 of the address of the look-up table for port C.
Table 103 - Port C Look Up Table Register
Address: 362h Label: portc_num_vpi_vci_bits Reset Value: 0000h Label num_vpi_vci_bits Bit Position 15:0 Type RW Description Indicates the total number of bits that are used to decode the look-up address for port C. 0001h = 1 bit used, FFFFh = 16 bits used. When subtracted from vci_n, this indicates the number of VPI bits used.
Table 104 - Port C VPI/VCI Identification Register
Address: 364h Label: portc_concatenation Reset Value: 0000h Label vci_nc reserved Bit Position 4:0 15:5 Type RW RW Description Indicates the number of VCI bits used to decode the look-up address for port C. Reserved. Must always be "0000_0000_000"
Table 105 - Port C Concatenation Register
Address: 368h Label: portc_vpi_match Reset Value: 0000h Label vpi_matchc Bit Position 11:0 Type RW Description For a cell from port C to be considered valid, any bits in its VPI whose corresponding bits in reg 34Ah are '1' must have the value contained in this register.
Table 106 - Port C VPI Match Register
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Zarlink Semiconductor Inc.
MT90503
Address: 368h Label: portc_vpi_match Reset Value: 0000h Label reserved Bit Position 15:12 Type RW Description Reserved. Must always be "0000"
Data Sheet
Table 106 - Port C VPI Match Register
Address: 36Ah Label: portc_vpi_mask Reset Value: 0000h Label vpi_maskc Bit Position 11:0 Type RW Description For a cell from port C to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 348h. Reserved. Must always be "0000"
reserved
15:12
RW
Table 107 - Port C VPI Mask Register
Address: 36Ch Label: portc_vci_match Reset Value: 0000h Label vci_matchc Bit Position 15:0 Type RW Description For a cell from port C to be considered valid, any bits in its VCI whose corresponding bits in reg 34Eh are '1' must have the value contained in this register.
Table 108 - Port C VCI Match Register
Address: 36Eh Label: portc_vci_mask Reset Value: 0000h Label vci_maskc Bit Position 15:0 Type RW Description For a cell from port C to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 34Ch.
Table 109 - Port C VCI Match Register
135
Zarlink Semiconductor Inc.
MT90503
Address: 370h Label: portc_cell_arrival_high Reset Value: 0000h Label ic_arr[31:16] Bit Position 15:0 Type CNT Description
Data Sheet
Freerunning counter of the number of cells received on port C.
Table 110 - Port C Cell Arrival Counter High Register
Address: 372h Label: portc_cell_arrival_low Reset Value: 0000h Label ic_arr[15:0] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells received on port C.
Table 111 - Port C Cell Arrival Counter Low Register
Address: 374h Label: portc_cell_departure_high Reset Value: 0000h Label oc_dep[31:16] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells transmitted on port C.
Table 112 - Port C Cell Departure Counter High Register
Address: 376h Label: portc_cell_departure_low Reset Value: 0000h Label oc_dep[15:0] Bit Position 15:0 Type CNT Description Freerunning counter of the number of cells transmitted on port C.
Table 113 - Port C Cell Departure Counter Low Register
136
Zarlink Semiconductor Inc.
MT90503
Address: 378h Label: portc_overflow0 Reset Value: 0000h Label ic_rx_cell_max Bit Position 4:0 Type RW Description
Data Sheet
If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port A output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port B output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0"
ic_oa_cell_max
9:5
RW
ic_ob_cell_max
14:10
RW
reserved
15
RW
Table 114 - Port C Overflow0 Register
Address: 37Ah Label: portc_overflow1 Reset Value: 0000h Label ic_oc_cell_max Bit Position 4:0 Type RW Description If the cell fill of the Port C output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0000_0000_000"
reserved
15:5
RW
Table 115 - Port C Overflow1 Register
Address: 390h Label: tx_sar_cell_arrival_high Reset Value: 0000h Label tx_arr[31:16] Bit Position 15:0 Type CNT Description Bits [31:16] of TX SAR arrival cell counter. Counts the number of cells received by UTOPIA from the TX SAR
Table 116 - TX_SAR Cell Arrival Counter High Register
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Zarlink Semiconductor Inc.
MT90503
Address: 392h Label: tx_sar_cell_arrival_low Reset Value: 0000h Label tx_arr[15:0] Bit Position 15:0 Type CNT Description
Data Sheet
Bits [15:0] of TX SAR arrival cell counter. Counts the number of cells received by UTOPIA from the TX SAR
Table 117 - TX_SAR Cell Arrival Counter Low Register Address: 394h Label: rx_sar_cell_departure_high Reset Value: 0000h Label rx_dep[31:16] Bit Position 15:0 Type CNT Description Bits [31:16] of RX SAR departure cell counter. Counts the number of cells sent to the RX SAR from UTOPIA
Table 118 - RX_SAR Cell Departure Counter High Register
Address: 396h Label: rx_sar_cell_departure_low Reset Value: 0000h Label rx_dep[15:0] Bit Position 15:0 Type CNT Description Bits [15:0] of RX SAR departure cell counter. Counts the number of cells sent to the RX SAR from UTOPIA
Table 119 - RX_SAR Cell Departure Counter Low Register
Address: 398h Label: tx_sar_overflow Reset Value: 0000h Label tx_rx_cell_max Bit Position 4:0 Type RW Description If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port A output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. 0h = no backpressure If the cell fill of the Port B output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0"
tx_oa_cell_max tx_ob_cell_max reserved
9:5 14:10 15
RW RW RW
Table 120 - TX_SAR Overflow0 Register
138
Zarlink Semiconductor Inc.
MT90503
Address: 39Ah Label: tx_sar_overflow Reset Value: 0000h Label tx_oc_cell_max Bit Position 4:0 Type RW Description
Data Sheet
If the cell fill of the Port C output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. 0h = no backpressure Reserved. Must always be "0000_0000_000"
reserved
15:5
RW
Table 121 - TX_SAR Overflow1 Register
Address: 3A0h Label: hec_byte_control Reset Value: 0055h Label hec_mask reserved Bit Position 7:0 15:8 Type RW RW Description Value by which the HEC generated on UTOPIA will be XORed before being transmitted. Should match the value used by the PHY. Reserved. Must always be "0000_0000_0"
Table 122 - HEC Byte Control Register
Address: 3A2h Label: unknown_header_routing Reset Value: 0000h Label rxa_ncr Bit Position 3:0 Type RW Description Normal cell routing for unknow cells received on port A. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. Normal cell routing for unknow cells received on port B. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. Normal cell routing for unknow cells received on port C. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. Reserved. Must always be "0000"
rxb_ncr
7:4
RW
rxc_ncr
11:8
RW
reserved
15:12
RW
Table 123 - Unknown Header Routing Register
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Zarlink Semiconductor Inc.
MT90503
Address: 3A4h Label: unknown_oam_routing Reset Value: 0000h Label rxa_ocr Bit Position 3:0 Type RW Description
Data Sheet
OAM cell routing for unknow cells received on port A. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. OAM cell routing for unknow cells received on port B. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. OAM cell routing for unknow cells received on port C. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. Reserved. Must always be "0000"
rxb_ocr
7:4
RW
rxc_ocr
11:8
RW
reserved
15:12
RW
Table 124 - Unknown OAM Routing Register
Address: 3C0h Label: gpio_input0 Reset Value: 0000h Label txa_data_input rxa_data_input Bit Position 7:0 15:8 Type RO RO Description Current level of txa_data pins [15:8] Current level of rxa_data pins [15:8]
Table 125 - GPIO Input0 Register
Address: 3C2h Label: gpio_input1 Reset Value: 0000h Label txb_data_input rxb_data_input Bit Position 7:0 15:8 Type RO RO Description Current level of txb_data pins [15:8] Current level of rxb_data pins [15:8]
Table 126 - GPIO Input1 Register
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Zarlink Semiconductor Inc.
MT90503
Address: 3C4h Label: gpio_input2 Reset Value: 0000h Label phya_alm_input phyb_alm_input phya_tx_led_input phya_rx_led_input phyb_tx_led_input phyb_rx_led_input reserved Bit Position 0 1 2 3 4 5 15:6 Type RO RO RO RO RO RO RO Description Current level of phya_alm pin Current level of phya_alm pin Current level of phya_tx_led pin Current level of phya_rx_led pin Current level of phyb_tx_led pin Current level of phyb_rx_led pin Reserved. Always read as "0000_0000_00"
Data Sheet
Table 127 - GPIO Input2 Register Address: 3C8h Label: txa_data_status Reset Value: 0000h Label txa_data8_rise txa_data8_fall txa_data9_rise txa_data9_fall txa_data10_rise txa_data10_fall txa_data11_rise txa_data11_fall txa_data12_rise txa_data12_fall txa_data13_rise txa_data13_fall txa_data14_rise txa_data14_fall txa_data15_rise txa_data15_fall Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0'
Table 128 - TXA Data Status Register
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Address: 3CAh Label: txa_data_status_ie Reset Value: 0000h Label txa_data8_rise_ie txa_data8_fall_ie txa_data9_rise_ie txa_data9_fall_ie txa_data10_rise_ie txa_data10_fall_ie txa_data11_rise_ie txa_data11_fall_ie txa_data12_rise_ie txa_data12_fall_ie txa_data13_rise_ie txa_data13_fall_ie txa_data14_rise_ie txa_data14_fall_ie txa_data15_rise_ie txa_data15_fall_ie Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type IE IE IE IE IE IE IE IE IE IE IE IE IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 129 - TXA Data Interrupt Enable Register
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Address: 3CCh Label: rxa_data_status Reset Value: 0000h Label rxa_data8_rise rxa_data8_fall rxa_data9_rise rxa_data9_fall rxa_data10_rise rxa_data10_fall rxa_data11_rise rxa_data11_fall rxa_data12_rise rxa_data12_fall rxa_data13_rise rxa_data13_fall rxa_data14_rise rxa_data14_fall rxa_data15_rise rxa_data15_fall Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description
Data Sheet
This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0'
Table 130 - RXA Data Status Register
Address: 3CEh Label: rxa_data_status_ie Reset Value: 0000h Label rxa_data8_rise_ie rxa_data8_fall_ie rxa_data9_rise_ie Bit Position 0 1 2 Type IE IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 131 - RXA Data Interrupt Enable Register
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Address: 3CEh Label: rxa_data_status_ie Reset Value: 0000h Label rxa_data9_fall_ie rxa_data10_rise_ie rxa_data10_fall_ie rxa_data11_rise_ie rxa_data11_fall_ie rxa_data12_rise_ie rxa_data12_fall_ie rxa_data13_rise_ie rxa_data13_fall_ie rxa_data14_rise_ie rxa_data14_fall_ie rxa_data15_rise_ie rxa_data15_fall_ie Bit Position 3 4 5 6 7 8 9 10 11 12 13 14 15 Type IE IE IE IE IE IE IE IE IE IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 131 - RXA Data Interrupt Enable Register (continued) Address: 3D0h Label: txb_data_status Reset Value: 0000h Label txb_data8_rise txb_data8_fall txb_data9_rise Bit Position 0 1 2 Type ROL ROL ROL Description This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1'
Table 132 - TXB Data Status Register
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Address: 3D0h Label: txb_data_status Reset Value: 0000h Label txb_data9_fall txb_data10_rise txb_data10_fall txb_data11_rise txb_data11_fall txb_data12_rise txb_data12_fall txb_data13_rise txb_data13_fall txb_data14_rise txb_data14_fall txb_data15_rise txb_data15_fall Bit Position 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description
Data Sheet
This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0'
Table 132 - TXB Data Status Register (continued)
Address: 3D2h Label: txb_data_status_ie Reset Value: 0000h Label txb_data8_rise_ie txb_data8_fall_ie txb_data9_rise_ie txb_data9_fall_ie txb_data10_rise_ie Bit Position 0 1 2 3 4 Type IE IE IE IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 133 - TXB Data Interrupt Enable Register
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Address: 3D2h Label: txb_data_status_ie Reset Value: 0000h Label txb_data10_fall_ie txb_data11_rise_ie txb_data11_fall_ie txb_data12_rise_ie txb_data12_fall_ie txb_data13_rise_ie txb_data13_fall_ie txb_data14_rise_ie txb_data14_fall_ie txb_data15_rise_ie txb_data15_fall_ie Bit Position 5 6 7 8 9 10 11 12 13 14 15 Type IE IE IE IE IE IE IE IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 133 - TXB Data Interrupt Enable Register (continued)
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Address: 3D4h Label: rxb_data_status Reset Value: 0000h Label rxb_data8_rise rxb_data8_fall rxb_data9_rise rxb_data9_fall rxb_data10_rise rxb_data10_fall rxb_data11_rise rxb_data11_fall rxb_data12_rise rxb_data12_fall rxb_data13_rise rxb_data13_fall rxb_data14_rise rxb_data14_fall rxb_data15_rise rxb_data15_fall Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description
Data Sheet
This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0'
Table 134 - RXB Data Status Register
Address: 3D6h Label: rxb_data_status_ie Reset Value: 0000h Label
rxb_data8_rise_ie rxb_data8_fall_ie rxb_data9_rise_ie rxb_data9_fall_ie
Bit Position
0 1 2 3
Type
IE IE IE IE
Description
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 135 - RXB Data Interrupt Enable Register
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rxb_data10_rise_ie rxb_data10_fall_ie rxb_data11_rise_ie rxb_data11_fall_ie rxb_data12_rise_I rxb_data12_fall_ie rxb_data13_rise_ie rxb_data13_fall_ie rxb_data14_rise_ie rxb_data14_fall_ie rxb_data15_rise_ie rxb_data15_fall_ie 4 5 6 7 8 9 10 11 12 13 14 15 IE IE IE IE IE IE IE IE IE IE IE IE
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 135 - RXB Data Interrupt Enable Register (continued)
Address: 3D8h Label: gpio_status Reset Value: 0000h Label phya_alm_rise phya_alm_fall phyb_alm_rise phyb_alm_fall phya_tx_led_rise phya_tx_led_fall phya_rx_led_rise phya_rx_led_fall phyb_tx_led_rise Bit Position 0 1 2 3 4 5 6 7 8 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL Description This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1'
Table 136 - GPIO Status Register
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Address: 3D8h Label: gpio_status Reset Value: 0000h Label phyb_tx_led_fall phyb_rx_led_rise phyb_rx_led_fall reserved Bit Position 9 10 11 15:12 Type ROL ROL ROL ROL Description
Data Sheet
This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' Reserved. Always read as "0000"
Table 136 - GPIO Status Register (continued)
Address: 3DAh Label: gpio_status_ie Reset Value: 0000h Label phya_alm_rise_ie phya_alm_fall_ie phyb_alm_rise_ie phyb_alm_fall_ie phya_tx_led_rise_ie phya_tx_led_fall_ie phya_rx_led_rise_ie phya_rx_led_fall_ie phyb_tx_led_rise_ie phyb_tx_led_fall_ie phyb_rx_led_rise_ie phyb_rx_led_fall_ie Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 Type IE IE IE IE IE IE IE IE IE IE IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated.
Table 137 - GPIO Status Register
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Address: 3DAh Label: gpio_status_ie Reset Value: 0000h Label reserved Bit Position 15:12 Type RO Description Reserved. Always read as "0000"
Data Sheet
Table 137 - GPIO Status Register (continued)
Address: 3E0h Label: gpio_output0 Reset Value: 0000h Label txa_data_output reserved Bit Position 7:0 15:8 Type RW RW Description This is the value sent out on the pins txa_data [15:8], used in conjuction with the OE bit Reserved. Must always be "0000_0000"
Table 138 - GPIO Output0 Register
Address: 3E2h Label: gpio_output1 Reset Value: 0000h Label txb_data_output reserved Bit Position 7:0 15:8 Type RW RW Description This is the value sent out on the pins txb_data [15:8], used in conjuction with the OE bit Reserved. Must always be "0000_0000"
Table 139 - GPIO Output1 Register
Address: 3E4h Label: gpio_output2 Reset Value: 0000h Label phya_tx_led_output phya_rx_led_output Bit Position 0 1 Type RW RW Description This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit
Table 140 - GPIO Output2 Register
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Address: 3E4h Label: gpio_output2 Reset Value: 0000h Label phyb_tx_led_output phyb_rx_led_output reserved Bit Position 2 3 15:4 Type RW RW RW Description
Data Sheet
This is the value sent out on the corresponding pin, used in conjuction with the OE bit This is the value sent out on the corresponding pin, used in conjuction with the OE bit Reserved. Must always be "0000_0000_0000"
Table 140 - GPIO Output2 Register (continued)
Address: 3E8h Label: gpio_oe0 Reset Value: 0000h Label txa_data_oe reserved Bit Position 7:0 15:8 Type RW RW Description This is OE bit used to drive the txa_data [15:8] pins Reserved. Must always be "0000_0000"
Table 141 - GPIO Output Enable0 Register
Address: 3EAh Label: gpio_oe1 Reset Value: 0000h Label txb_data_oe reserved Bit Position 7:0 15:8 Type RW RW Description This is OE bit used to drive the txb_data [15:8] pins Reserved. Must always be "0000_0000"
Table 142 - GPIO Output Enable1 Register
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Zarlink Semiconductor Inc.
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Address: 3ECh Label: gpio_oe2 Reset Value: 0000h Label phya_tx_led_oe phya_rx_led_oe phyb_tx_led_oe phyb_rx_led_oe reserved Bit Position 0 1 2 3 15:4 Type RW RW RW RW RW Description
Data Sheet
This is OE bit used to drive the corresponding pin This is OE bit used to drive the corresponding pin This is OE bit used to drive the corresponding pin This is OE bit used to drive the corresponding pin Reserved. Must always be "0000_0000_0000"
Table 143 - GPIO Output Enable2 Register
5.5.4
TDM Registers
Address: 400h Label: control Reset Value: 0000h Label global_oe h100_data_loopback tdmie_enable stream_mode Bit Position 0 1 2 4:3 Type RW RW RW RW Description '0' = ct_d[31:0] forced tri-state; '1' = ct_d[31:0] may be driven. '0' = no ct_d[31:0] loopback; '1' = ct_d[31:0] loopback. For test only. '0' disables TDM process. Should only be set to '1' when CAM has been programmed "00" = 32 streams, "01" = 16 streams, "10" = 4 streams, "11" = reserved. This register is only used for tests: in real operation, it should be left to "00" (32 streams). Reserved. Must always be "0000_0000_00" When '1', all the status bits in the register will be set.
reserved test_status
14:5 15
RW TS
Table 144 - TDM Control Register
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Zarlink Semiconductor Inc.
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Address: 402h Label: status0 Reset Value: 0000h Label tdm_out_of_bandwidth0 cut_vc_detected underrun_detected cas_underrun_detected rdatamem_overflow tdmtxpip_overflow tdmrxpip_overflow reserved Bit Position 0 1 2 3 4 5 6 15:7 Type ROL ROL ROL ROL ROL ROL ROL ROL Description
Data Sheet
Indicates that the TDM state machine is out of bandwidth. Fatal chip error, usually due to mclk frequency being too low. This bit is set when 255 underruns are detected on a VC whose CAM entry has an enabled "Cut VC status enable" bit Underrun reported on a voice channel on the ATM link. Underrun reported on CAS bits on the ATM link. Overflow in the TDM RX internal data memory. Fatal chip error. Overflow in the TDM TX data memory access cache. Fatal chip error. Overflow in the TDM RX data memory access cache. Fatal chip error. Reserved. Always read as "0000_0000_0"
Table 145 - TDM Status Register
Address: 408h Label: cut_vc_tsst Reset Value: 0000h Label tsst_number_cut_vc reserved Bit Position 11:0 15:12 Type RO RO Description Indicates the TSST on which the last cut VC error occurred. Reserved. Always read as "0000"
Table 146 - Cut VC TSST Register
Address: 40Ah Label: underrun_tsst Reset Value: 0000h Label tsst_number_underrun reserved Bit Position 11:0 15:12 Type RO RO Description Indicates the TSST on which the last underrun error occurred. Reserved. Always read as "0000"
Table 147 - TSST Underrun Register
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Address: 40Ch Label: cas_underrun_tsst Reset Value: 0000h Label tsst_number_cas_underrun reserved Bit Position 11:0 15:12 Type RO RO
Data Sheet
Description Indicates the TSST on which the last CAS underrun error occurred. Reserved. Always read as "0000"
Table 148 - TSST CAS Underrun Register
Address: 410h Label: tdmint_reg0 Reset Value: 0000h Label h100_samp_clk_delay_flops h100_samp_clk_delay_buff h100_oe_clk_delay_flops h100_oe_clk_delay_buff Bit Position 3:0 7:4 11:8 15:12 Type RW RW RW RW Description Number of flops used = 8 + value of this register. "1111" is reserved for selecting falling edge ct_c8 clock. "1111" is reserved for selecting rising edge ct_c8 clock Number of flops used = 8 + value of this register Number of delay buffers used in the delay chain.
Table 149 - TDM Interrupt 0 Register
Address: 412h Label: tdmint_reg1 Reset Value: 0000h Label h100_ts_counter_timeout h100_oe_override_disable dstream_0_3_freq dstream_4_7_freq dstream_8_11_freq Bit Position 6:0 7 9:8 11:10 13:12 Type RW RW RW RW RW Description Number of mclk cycles in 8 ct_c8 clock cycles - 10% '1' = do not tri-state the ct_d pin after every timeslot. To respect the H.100 standard, this should be left to '0'. ct_d[3:0] stream clock speed. "00" = 2.048 Mhz; "01" = 4.096 MHz; "10" = 8.192 MHz; "11" = reserved. ct_d[7:4] stream clock speed. "00" = 2.048 Mhz; "01" = 4.096 MHz; "10" = 8.192 MHz; "11" = reserved. ct_d[11:8] stream clock speed. "00" = 2.048 Mhz; "01" = 4.096 MHz; "10" = 8.192 MHz; "11" = reserved.
Table 150 - TDM Interrupt 1 Register
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Address: 412h Label: tdmint_reg1 Reset Value: 0000h Label dstream_12_15_freq Bit Position 15:14 Type RW Description
Data Sheet
ct_d[15:12] stream clock speed. "00" = 2.048 Mhz; "01" = 4.096 MHz; "10" = 8.192 MHz; "11" = reserved.
Table 150 - TDM Interrupt 1 Register (continued)
Address: 420h Label: tdmie_misc Reset Value: 00FFh Label null_byte cas_enable_position Bit Position 7:0 10:8 Type RW RW Description Null byte with which the chip will pad if underruns occur and null byte padding is chosen. Position of the CAS enable bit within the byte on the TDM bus. The CAS nibble will be contained in the nibble in which the enable is not present. For example, if the enable is contained in bit 6, then the nibble will be in bits 3:0. Polarity of the CAS enable bit on the TDM bus. Reserved. Must always be "0000"
cas_enable_polarity reserved
11 15:12
RW RW
Table 151 - TDM Interrupt Enable Misc. Register
Address: 460h Label: pnt_ro Reset Value: 0000h Label txsar_write_pnt_pcm_monitor [9:0] reserved Bit Positio n 9:0 15:10 Type RO RO Description The current value of the TDM write pointer sent to the TX SAR. Only used for tests. Reserved. Always read as "0000_00"
Table 152 - TDM Write Pointer 0 Register
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Address: 462h Label: txsar_pnt_fire Reset Value: 0000h Label txsar_write_pnt_insert[9:0] txsar_write_pnt_insert_ena reserved Bit Positio n 9:0 10 15:11 Type RW RW RO Description
Data Sheet
The test value of the TDM write pointer sent to the TX SAR. Only used for tests. When '1', the above pointer will be sent to the TX SAR instead of the valid pointer. Only used for tests. Reserved. Always read as "0000_00"
Table 153 - TDM Write Pointer 1 Register
Address: 464h Label: rxsar_pnt_fire Reset Value: 0000h Label rxsar_write_pnt_insert[14:0] rxsar_write_pnt_insert_ena Bit Position 14:0 15 Type RW RW Description The test value of the TDM read pointer sent to the RX SAR. Only used for tests. When '1', the above pointer will be sent to the RX SAR instead of the valid pointer. Only used for tests.
Table 154 - TDM Read Pointer Register
5.5.5
TX_SAR Registers
Address: 500h Label: control Reset Value: 0000h Label reserved test_status Bit Position 14:0 15 Type RO TS Description Reserved. Always read as "0000_0000_0000_000" When '1', all the status bits in the register will be set.
Table 155 - TX_SAR Control Register
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Address: 502h Label: status Reset Value: 0000h Label global_tx_slip Bit Position 0 Type ROL Description
Data Sheet
Raised when a bad configuration of the offset field in the TX control structure causes the TX SAR to read data that has not been written yet. Overflow in the TX SAR data memory access cache. Fatal chip error. Reserved. Always read as "0000_0000_0000_00"
txsarpip_overflow reserved
1 15:2
ROL RO
Table 156 - TX_SAR Status Register
Address: 504h Label: status_ie Reset Value: 0000h Label global_tx_slip_ie txsarpip_overflow_ie reserved Bit Position 0 1 15:2 Type IE IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as ""0000_0000_0000_00"
Table 157 - TX_SAR Interrupt Enable Register
Address: 506h Label: control1 Reset Value: 0000h Label reset_band_per reserved Bit Position 0 15:1 Type PUL RO Resets the band_per register field. Reserved. Always read as "0000_0000_0000_000" Description
Table 158 - TX_SAR Control 1 Register
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Address: 508h Label: data_cell_read Reset Value: 0000h Label data_read_pnt reserved Bit Position 13:0 15:14 Type RO RO Description Chip's read pointer to the AAL0 FIFO. Reserved. Always read as "00"
Data Sheet
Table 159 - TX_SAR Data Read Pointer Register
Address: 50Ah Label: data_cell_write Reset Value: 0000h Label data_write_pnt reserved Bit Position 13:0 15:14 Type RW RW Description CPU's write pointer to the AAL0 FIFO. Reserved. Must always be "00"
Table 160 - TX_SAR Data Write Pointer Register
Address: 50Ch Label: data_cell_add Reset Value: 0000h Label data_add reserved Bit Position 13:0 15:14 Type RW RW Description Bits 19:6 of the address of the FIFO in external memory Reserved. Always read as "00"
Table 161 - TX_SAR Data Address Register
Address: 50Eh Label: data_cell_size Reset Value: 0000h Label data_size reserved Bit Position 13:0 15:14 Type RW RW Description Size of data cell FIFO in 1 cell increments. All zeros = 16k cells. Minimum 4 cells. Reserved. Must always be "00"
Table 162 - TX_SAR Data Cell Size Register
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Address: 510h Label: percentage_of_bandwidth Reset Value: 0000h Label band_per Bit Position 15:0 Type RO Description
Data Sheet
Monitor of the maximum number of mclk cycles that it has taken the chip to treat an entire TX SAR frame. If this number is greater than mclk (in Hz) / 8000, some of the frames are overloaded.
Table 163 - Percent of Bandwidth Register
5.5.6
Scheduler Registers
Address: 600h Label: control Reset Value: 0000h Label test_status Bit Position 15 Type TS Description When '1', all the status bits in the register will be set.
Table 164 - Scheduler Test Status Register
Address: 602h Label: status Reset Value: 0000h Label out_of_band Bit Position 0 Type ROL Description Indicates that the wheel treatment is more than fr_late frames late. This means that at least some of the frames in the wheels are overloaded. Reserved. Always read as "0000_0000_0000_000"
reserved
15:1
ROL
Table 165 - Scheduler Status Register
Address: 604h Label: status_ie Reset Value: 0000h Label out_of_band_ie reserved Bit Position 0 15:1 Type IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as "0000_0000_0000_000"
Table 166 - Scheduler Interrupt Enable Register
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Address: 608h Label: frame_latency Reset Value: 0001h Label fr_late reserved Bit Position 3:0 15:4 Type RW RW Description
Data Sheet
Number of frames by which the chip is allowed to be late. 0h = illegal. Reserved. Must always be "0000_0000_0000"
Table 167 - Frame Latency Register
Address: 610h Label: wheel_info _0 Reset Value: 0001h Label wheel0_ena wheel0_inf wheel1_ena wheel1_inf wheel2_ena wheel2_inf wheel3_ena wheel3_inf Bit Position 0 3:1 4 7:5 8 11:9 12 15:13 Type RW RW RW RW RW RW RW RW Enable for wheel 0. Configuration of wheel 0. "000" = normal, "100" = T1, "101" = E1, others reserved.l Enable for wheel 1. Configuration of wheel 1. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 2. Configuration of wheel 2. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 3. Configuration of wheel 3. "000" = normal, "100" = T1, "101" = E1, others reserved. Description
Table 168 - Scheduler Configuration & Enable 0 Register
Address: 612h Label: wheel_inf_1 Reset Value: 0000h Label wheel4_ena wheel4_inf Bit Position 0 3:1 Type RW RW Enable for wheel 4. Configuration of wheel 4. "000" = normal,"100" = T1, "101" = E1, others reserved. Description
Table 169 - Scheduler Configuration & Enable 1 Register
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Address: 612h Label: wheel_inf_1 Reset Value: 0000h Label wheel5_ena wheel5_inf wheel6_ena wheel6_inf wheel7_ena wheel7_inf Bit Position 4 7:5 8 11:9 12 15:13 Type RW RW RW RW RW RW Enable for wheel 5. Description
Data Sheet
Configuration of wheel 5. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 6. Configuration of wheel 6. "000" = normal,"100" = T1, "101" = E1, others reserved Enable for wheel 7. Configuration of wheel 7. "000" = normal, "100" = T1, "101" = E1, others reserved.
Table 169 - Scheduler Configuration & Enable 1 Register (continued)
Address: 614h Label: wheel_inf_2 Reset Value: 0000h Label wheel8_ena wheel8_inf wheel9_ena wheel9_inf wheelA_ena wheelA_inf wheelB_ena wheelB_inf Bit Position 0 3:1 4 7:5 8 11:9 12 15:13 Type RW RW RW RW RW RW RW RW Enable for wheel 8. Configuration of wheel 8. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 9. Configuration of wheel 9. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 10. Configuration of wheel 10. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 11. Configuration of wheel 11. "000" = normal, "100" = T1, "101" = E1, others reserved. Description
Table 170 - Scheduler Configuration & Enable 2 Register
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Address: 616h Label: wheel_inf_3 Reset Value: 0000h Label wheelC_ena wheelC_inf wheelD_ena wheelD_inf wheelE_ena wheelE_inf reserved Bit Position 0 3:1 4 7:5 8 11:9 15:12 Type RW RW RW RW RW RW RW Enable for wheel 12. Description
Data Sheet
Configuration of wheel 12. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 13. Configuration of wheel 13. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 14. Configuration of wheel 14. "000" = normal, "100" = T1, "101" = E1, others reserved. Reserved. Must always be "0000"
Table 171 - Scheduler Configuration & Enable 3 Register
5.5.7
RX_SAR Registers
Address: 700h Label: control Reset Value: 0000h Label always_diagnose reserved test_status Bit Position 0 14:1 15 Type RW RW TS Description When '1', an error report structure will be generated for every cell that arrives. Used for tests. Reserved. Must always be "0000_0000_0000_00" When '1', all the status bits in the register will be set.
Table 172 - RX_SAR Control Register
Address: 702h Label: status Reset Value: 0000h Label rxsarpip_overflow data_fifo_overflow Bit Position 0 1 Type ROL ROL Description Overflow in the RX SAR data memory access cache. Fatal chip error. Overflow in the data cell FIFO in external memory.
Table 173 - RX_SAR Status Register
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Address: 702h Label: status Reset Value: 0000h Label error_fifo_overflow reserved Bit Position 2 15:3 Type ROL ROL Description
Data Sheet
Overflow in the error report structure FIFO in external memory. Reserved. Always read as "0000_0000_0000_0"
Table 173 - RX_SAR Status Register (continued)
Address: 704h Label: status_ie Reset Value: 0000h Label rxsarpip_overflow_ie data_fifo_overflow_ie error_fifo_overflow_ie reserved Bit Position 0 1 2 15:3 Type IE IE IE IE Description When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as "0000_0000_0000_0"
Table 174 - RX_SAR Interrupt Enable Register
Address: 00708h Label: data_cell_read Reset Value: 0000h Label data_read_pnt reserved Bit Position 13:0 15:14 Type RW RW Description The CPU's read pointer to the AAL0 cell FIFO. Reserved. Must always be "00"
Table 175 - RX_SAR Data Read Pointer Register
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Address: 70Ah Label: data_cell_write Reset Value: 0000h Label data_write_pnt reserved Bit Position 13:0 15:14 Type RO RO Description
Data Sheet
The chip's write pointer to the AAL0 cell FIFO. Reserved. Always read as "00"
Table 176 - RX_SAR Data Write Pointer Register
Address: 70Ch Label: data_cell_add Reset Value: 0000h Label data_add reserved Bit Position 13:0 15:14 Type RW RW Description Bits 19:6 of the address of the FIFO in external memory Reserved. Must always be "00"
Table 177 - RX_SAR Data Address Register
Address: 70Eh Label: data_cell_size Reset Value: 0000h Label data_size reserved Bit Position 13:0 15:14 Type RW RW Description Size of data cell FIFO in 1 cell increments. All zeros = 16k cells. Reserved. Must always be "00"
Table 178 - RX_SAR Data Cell Size Register
Address: 710h Label: error_struct_read Reset Value: 0000h Label error_read_pnt Bit Position 15:0 Type RW Description The CPU's read pointer to the error report structure FIFO.
Table 179 - Error Structure Read Register
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Address: 712h Label: error_struct_write Reset Value: 0000h Label error_write_pnt Bit Position 15:0 Type RO Description
Data Sheet
The chip's write pointer to the error report structure FIFO.
Table 180 - Error Structure Write Register
Address: 714h Label: error_struct_add_high Reset Value: 0000h Label error_add[16] reserved Bit Position 0 15:1 Type RW RW Description Bits 19:3 of the address of the error FIFO in external memory Reserved. Must always be "0000_0000_0000_000"
Table 181 - Error Structure Address High Register
Address: 716h Label: error_struct_add_low Reset Value: 0000h Label error_add[15:0] Bit Position 15:0 Type RW Description Bits 19:3 of the address of the error FIFO in external memory
Table 182 - Error Structure Address Low Register
Address: 718h Label: error_struct_size Reset Value: 0000h Label error_size Bit Position 15:0 Type RW Description Size of the error structure FIFO (in number of error structures, 8-bytes each).
Table 183 - Error Structure Size Register
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Address: 720h Label: aal0_timeout_high Reset Value: 0000h Label aal0_timeout_period[19:16] reserved Bit Position 3:0 15:4 Type RW RW Description
Data Sheet
Time, in us, that an AAL0 cell can wait in the FIFO before an alarm is generated. Reserved. Must always be "0000_0000_0000"
Table 184 - AAL0 Timeout High Register
Address: 722h Label: aal0_timeout_low Reset Value: 0000h Label aal0_timeout_period[15:0 ] Bit Position 15:0 Type RW Description Time, in us, that an AAL0 cell can wait in the FIFO before an alarm is generated.
Table 185 - AAL0 Timeout Low Register
Address: 724h Label: error_timeout_high Reset Value: 0000h Label error_timeout_period[19:16] reserved Bit Position 3:0 15:4 Type RW RW Description Time, in us, that an error structure can wait in the FIFO before an alarm is generated. Reserved. Must always be "0000_0000_0000"
Table 186 - Error Timeout High Register
Address: 726h Label: error_timeout_low Reset Value: 0000h Label error_timeout_period[15:0] Bit Position 15:0 Type RW Description Time, in us, that an error structure can wait in the FIFO before an alarm is generated.
Table 187 - Error Timeout Low Register
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Address: 730h Label: treated_pulses Reset Value: 0000h Label aal0_treated_pulse Bit Position 0 Type PUL Description
Data Sheet
Written to '1' to indicate that AAL0 cell FIFO has been treated. Another alarm will not be generated until the above timeout has elapsed. Written to '1' to indicate that error structure FIFO has been treated. Another alarm will not be generated until the above timeout has elapsed. Reserved. Always read as "0000_0000_0000_00"
error_treated_pulse
1
PUL
reserved
15:2
PUL
Table 188 - Treated Pulses Register
5.5.8
Clock Registers
Address: 800h Label: control Reset Value: 0000h Label reserved test_status Bit Position 14:0 15 Type RO TS Description Reserved. Always Read as "0000_0000_0000_00" When '1', all the status bits in the register will be set.
Table 189 - Clock Control Register
Address: 802h Label: status Reset Value: 0000h Label mclk_count_alarm0 mclk_count_alarm1 mclk_count_alarm2 reserved Bit Position 0 1 2 15:3 Type ROL ROL ROL ROL Description Indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm0 field. Indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm1 field. Indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm2 field. Reserved. Always read as "0000_0000_0000_0"
Table 190 - Clock Status Register
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Address: 804h Label: status_ie Reset Value: 0000h Label mclk_count_alarm0_ie mclk_count_alarm1_ie mclk_count_alarm2_ie reserved Bit Position 0 1 2 15:3 Type IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "0000_0000_0000_0"
Table 191 - Status Interrupt Enable Register
Address: 806h Label: mclk_count_high_alm0 Reset Value: 0000h Label mclk_count_high_alarm0 Bit Position 15:0 Type RW Description This register in conjuction with an interrupt enable can be used as a scheduler or as a Periodic Interrupt Controler.
Table 192 - MCLK Alarm 0 Register
Address: 808h Label: mclk_count_high Reset Value: 0000h Label mclk_count[31:16] Bit Position 15:0 Type RO Description Freerunning counter of mclk.
Table 193 - MCLK Counter High Register
Address: 80Ah Label: mclk_count_low Reset Value: 0000h Label mclk_count[15:0] Bit Position 15:0 Type RO Description Freerunning counter of mclk.
Table 194 - MCLK Counter Low Register
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Address: 80Ch Label: mclk_count_high_alm1 Reset Value: 0000h Label mclk_count_high_alarm1 Bit Position 15:0 Type RW Description
Data Sheet
This register in conjuction with an interrupt enable can be used as a scheduler or as a Periodic Interrupt Controller.
Table 195 - MCLK Alarm 1 Register
Address: 80Eh Label: mclk_count_high_alm2 Reset Value: 0000h Label mclk_count_high_alarm2 Bit Position 15:0 Type RW Description This register in conjuction with an interrupt enable can be used as a scheduler or as a Periodic Interrupt Controller.
Table 196 - MCLK Alarm 2 Register
Address: 810h Label: tx_srts_reg0 Reset Value: 0300h Label tx_srts_enable tx_srts_bus_clk_sel Bit Position 0 2:1 Type RW RW Description When '1', TX SRTS values will be generated at the rate indicated by the div_p and div_q registers. Selects which H.100 Bus clock will be used to generate SRTS. "0x"=ct_c8(which ever is used in slave timing) ; "10" = ct_c8_a; "11"=ct_c8_b. Reserved. Must always be "0000_0" Selects which pins must be used as the fnxi to generate the TX SRTS value. See Table 28, "Source Selection," on page 89 for a full description. Reserved. Must always be "00"
reserved tx_srts_fnxi_input_select
7:3 13:8
RW RW
reserved
15:14
RW
Table 197 - TX_SRTS 0 Register
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Address: 812h Label: tx_srts_reg1 Reset Value: 0000h Label tx_srts_overflow Bit Position 0 Type ROL Description
Data Sheet
This bit will be set by hardware if the number of TX SRTS values sent by the TX SRTS generation module is greater than the number of TX SRTS values read by the TX SAR. This bit will be set by hardware if the number of TX SRTS values sent by the TX SRTS generation module is smaller than the number of TX SRTS values read by the TX SAR. Reserved. Always read as "0000_0000_0000_00"
tx_srts_underflow
1
ROL
reserved
15:2
ROL
Table 198 - TX_SRTS 1 Register
Address: 814h Label: tx_srts_reg2 Reset Value: 0000h Label tx_srts_overflow_ie tx_srts_underflow_ie reserved Bit Position 0 1 15:2 Type IE IE IE Description When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "0000_0000_0000_00"
Table 199 - TX_SRTS 2 Register
Address: 818h Label: tx_srts_reg4 Reset Value: 0001h Label tx_srts_srts8m8c_div_p Bit Position 15:0 Type RW Description The 8.192 MHz clock on the H.100 bus (ct_c8) must be divided by a number K in order to match the interval of 8 SRTS carrying cells. For example, a 24 channel AAL1 structured fully filled channel would require a K of (375 / 24) = 15.625. K must then be converted to the values P and Q using the following equation: K = P / Q. No rouding errors must be made in this conversion.
Table 200 - TX_SRTS 4 Register
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Address: 81Ah Label: tx_srts_reg5 Reset Value: 0001h Label tx_srts_srts8m8c_div_q Bit Position 15:0 Type RW Description
Data Sheet
See Table 200, "TX_SRTS 4 Register," on page 170 for a descrption of tx_srts_srts8m8c_div_p.
Table 201 - TX_SRTS 5 Register
Address: 820h Label: adapsrts0_reg0 Reset Value: 0000h Label adapsrts0_adaptive_enable Bit Position 0 Type RW Description When '1', the RX Adaptive block 0 is activated. Received cells on VCs tagged as clock recovery VC 'A' will generate an Adaptive point that will be written to external memory. When '1', the RX SRTS block 0 is activated. Received SRTS values on VCs tagged as clock recovery VC 'A' will be written to external memory. Also, local SRTS value will be generated using of the H.100 clocks. When '1', this bit forces the CRC in the AAL1 Header to be ignored. CRC Errors are reported no matter the state of this bit. When '1', this bit forces the Parity bit in the AAL1 Header to be ignored. Parity Errors are reported no matter the state of this bit. When '1', this bit forces the Sequence Number t in the AAL1 Header to be ignored. Sequence Number Errors are reported no matter the state of this bit. This bit can be directly routed out on a recov_X pin in order to convey the state (good / bad) of the clock generated by the adapsrts block 0. When this bit is written to '1', the pclk_div and pclk_frc are loaded into the digital PLL used to synthesize the pclk. When '0', the digital PLL used to synthesize pclk is put in reset state. When '1', it is not longer in reset. Reserved. Must always be "0000_0000"
adapsrts0_rx_srts_enable
1
RW
adapsrts0_ignore_crc
2
RW
adapsrts0_ignore_parity
3
RW
adapsrts0_ignore_seq_num
4
RW
adapsrts0_pclk_loss
5
RW
adapsrts0_pclk_divisor_load_now
6
PUL
adapsrts0_pclk_divisor_reset reserved
7 15:8
RW RW
Table 202 - Adaptive SRTS0 0 Register
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Address: 822h Label: adapsrts0_reg1 Reset Value: 0000h Label adapsrts0_aal1_crc_error adapsrts0_aal1_bad_parity adapsrts0_single_cell_lost adapsrts0_multi_cell_lost adapsrts0_cell_misinserted adapsrts0_timeout_flag Bit Position 0 1 2 3 4 5 Type ROL ROL ROL ROL ROL RO Description
Data Sheet
Set when an AAL1-byte CRC error occurs on cells used in the adapsrts0 block. Set when an AAL1-byte parity error occurs on cells used in the adapsrts0 block. Set when a single cell loss error occurs on cells used in the adapsrts0 block. Set when a multiple cell loss error occurs on cells used in the adapsrts0 block. Set when a cell misinsertion error occurs on cells used in the adapsrts0 block. Set when a the interval between two cells used in the adapsrts0 block is greater than adapsrts0_time_out_period. This bit is automatically cleared by hardware when the timeout condition ceases. Set when a the interval between two cells used in the adapsrts0 block is greater than adapsrts0_time_out_period. Set when two consecutive remote SRTS value were received, and when the second value could not be stored because the interval was too short. Set when two consecutive local SRTS value were received, and when the second value could not be stored because the interval was too short. Reserved. Always read as "0000_000"
adapsrts0_timeout_pulse
6
ROL
adapsrts0_rx_srts_remote_overflo w adapsrts0_rx_srts_local_overflow
7
ROL
8
ROL
reserved
15:9
ROL
Table 203 - Adaptive SRTS0 1 Register
Address: 824h Label: adapsrts0_reg2 Reset Value: 0000h Label adapsrts0_aal1_crc_error_ie Bit Position 0 Type IE Description When '1' and the corresponding status bit is '1', and interrupt will be generated.
Table 204 - Adaptive SRTS0 2 Register
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Address: 824h Label: adapsrts0_reg2 Reset Value: 0000h Label adapsrts0_aal1_bad_parity_ie adapsrts0_single_cell_lost_ie adapsrts0_multi_cell_lost_ie adapsrts0_cell_misinserted_ie reserved adapsrts0_timeout_pulse_ie adapsrts0_rx_srts_remote_overflow_i e adapsrts0_rx_srts_local_overflow_ie reserved Bit Position 1 2 3 4 5 6 7 8 15:9 Type IE IE IE IE RO IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "0" When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "0000_000"
Table 204 - Adaptive SRTS0 2 Register (continued)
Address: 826h Label: adapsrts0_reg3 Reset Value: 0000h Label adapsrts0_ref_input_select Bit Position 5:0 Type RW Description In adaptive mode, this field indicates which events the adapsrts0 block will consider as a timing reference. Rising edges on the recov_X pins can be used. Cell arrival events on Clock Recovery VC A or B can be used. See Table 28, "Source Selection," on page 89" for more details. Reserved. Always read as "00" In SRTS mode, this selects the fnxi input used in the RX SRTS block. See Table 28, "Source Selection," on page 89" for more details. Reserved. Always read as "00"
reserved adapsrts0_rx_fnxi_input_select
7:6 13:8
RO RW
reserved
15:14
RO
Table 205 - Adaptive SRTS0 3 Register
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Address: 828h Label: adapsrts0_reg4 Reset Value: 0000h Label adapsrts0_time_out_period Bit Position 15:0 Type RW Description
Data Sheet
This value defines the time-out period between two cells in both adaptive and SRTS mode. Unit is 1024 mclk cycles. 0000h will disabled checking.
Table 206 - Adaptive SRTS0 4 Register
Address: 82Ah Label: adapsrts0_reg5 Reset Value: 0000h Label adapsrts0_adap_pnt_elim_x Bit Position 7:0 Type RW Description In adaptive mode, this value defined how many points will be deleted vs how many points will be kept and written to external memory. It is defined as "keep 1 point out of X". Reserved. Must always be "0000_0000"
reserved
15:8
RW
Table 207 - Adaptive SRTS0 5 Register
Address: 82Ch Label: adapsrts0_reg6 Reset Value: 0001h Label adapsrts0_srts8m8c_div_p Bit Position 15:0 Type RW Description The clock generated by the digital PLL (pclk at 8KHz) must be divided by a number K in order to match the interval of 8 SRTS carrying cells. For example, a 24 channel AAL1 structured fully filled channel would require a K of (375 / 24) = 15.625 . K must then be converted to the values P and Q using the following equation: K = P / Q. No rouding errors must be made in this conversion.
Table 208 - Adaptive SRTS0 6 Register
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Address: 82Eh Label: adapsrts0_reg7 Reset Value: 0001h Label adapsrts0_srts8m8c_div_q Bit Position 15:0 Type RW Description See adapsrts0_srts8m8c_div_p description.
Data Sheet
Table 209 - Adaptive SRTS0 7 Register
Address: 830h Label: adapsrts0_reg8 Reset Value: 2710h Label adapsrts0_pclk_div Bit Position 15:0 Type RW Description In order to generate pclk, mclk must be divided by a factor K. This factor is likely to be fractional. The integer part of K is written in the form X / 65536, where X is written in the adapsrts0_pclk_frc register.
Table 210 - Adaptive SRTS0 8 Register
Address: 832h Label: adapsrts0_reg9 Reset Value: 0000h Label adapsrts0_pclk_frc Bit Position 15:0 Type RW Description For a description see adapsrts0_pclk_div adapsrts0_pclk_div above.
Table 211 - Adaptive SRTS0 9 Register
Address: 840h Label: adapsrts1_reg0 Reset Value: 0000h Label adapsrts1_adaptive_enable adapsrts1_rx_srts_enable adapsrts1_ignore_crc adapsrts1_ignore_parity Bit Position 0 1 2 3 Type RW RW RW RW Description See adapsrts0 registers 820h to 83Eh.
Table 212 - Adaptive SRTS1 0 Register
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Address: 840h Label: adapsrts1_reg0 Reset Value: 0000h Label adapsrts1_ignore_seq_num adapsrts1_pclk_loss adapsrts1_pclk_divisor_load_now adapsrts1_pclk_divisor_reset reserved Bit Position 4 5 6 7 15:8 Type RW RW PUL RW RW Description
Data Sheet
Reserved. Must always be "0000_0000"
Table 212 - Adaptive SRTS1 0 Register (continued)
Address: 842h Label: adapsrts1_reg1 Reset Value: 0000h Label adapsrts1_aal1_crc_error adapsrts1_aal1_bad_parity adapsrts1_single_cell_lost adapsrts1_multi_cell_lost adapsrts1_cell_misinserted adapsrts1_timeout_flag adapsrts1_timeout_pulse adapsrts1_rx_srts_remote_overflow adapsrts1_rx_srts_local_overflow reserved Bit Position 0 1 2 3 4 5 6 7 8 15:9 Type ROL ROL ROL ROL ROL RO ROL ROL ROL ROL Reserved. Always read as "0000_000" Description See Address: 822h, Table 203, "Adaptive SRTS0 1 Register," on page 172.
Table 213 - Adaptive SRTS1 1Register
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Address: 844h Label: adapsrts1_reg2 Reset Value: 0000h Label adapsrts1_aal1_crc_error_ie adapsrts1_aal1_bad_parity_ie adapsrts1_single_cell_lost_ie adapsrts1_multi_cell_lost_ie adapsrts1_cell_misinserted_ie reserved adapsrts1_timeout_pulse_ie adapsrts1_rx_srts_remote_overflow_ie adapsrts1_rx_srts_local_overflow_ie reserved Bit Position 0 1 2 3 4 5 6 7 8 15:9 Type IE IE IE IE IE RO IE IE IE IE Description
Data Sheet
See "Address: 842h" on page 176.
Reserved. Always read as "0000_000"
Table 214 - Adaptive SRTS1 2 Register
Address: 846h Label: adapsrts1_reg3 Reset Value: 0000h Label adapsrts1_ref_input_select reserved adapsrts1_rx_fnxi_input_select reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description See "Address: 826h" on page 173.
Table 215 - Adaptive SRTS1 3 Register
Address: 848h Label: adapsrts1_reg4 Reset Value: 0000h Label adapsrts1_time_out_period Bit Position 15:0 Type RW Description See "Address: 828h" on page 174.
Table 216 - Adaptive SRTS1 4 Register
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Address: 84Ah Label: adapsrts1_reg5 Reset Value: 0001h Label adapsrts1_adap_pnt_elim_x reserved Bit Position 7:0 15:8 Type RW RW Reserved. Must always be "0000_0000" Description
Data Sheet
Table 217 - Adaptive SRTS1 5 Register
Address: 84Ch Label: adapsrts1_reg6 Reset Value: 0000h Label adapsrts1_srts8m8c_div_p Bit Position 15:0 Type RW Description See "Address: 82Ch" on page 174.
Table 218 - Adaptive SRTS1 6 Register
Address: 84Eh Label: adapsrts1_reg7 Reset Value: 0000h Label adapsrts1_srts8m8c_div_q Bit Position 15:0 Type RW Description See "Address: 82Eh" on page 175.
Table 219 - Adaptive SRTS1 7 Register
Address: 850h Label: adapsrts1_reg8 Reset Value: 0000h Label adapsrts1_pclk_div Bit Position 15:0 Type RW Description See "Address: 830h" on page 175.
Table 220 - Adaptive SRTS1 8 Register
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Address: 852h Label: adapsrts1_reg9 Reset Value: 0000h Label adapsrts1_pclk_frc Bit Position 15:0 Type RW Description See "Address: 832h" on page 175.
Data Sheet
Table 221 - Adaptive SRTS1 9 Register
Address: 860h Label: pinmux_reg0 Reset Value: 0202h Label pinmux_recov_b_sel reserved pinmux_recov_a_sel reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description This field selects the recov_b output. See "Clockrec Source Select" page for more details. Reserved. Always read as "00". This field selects the recov_a output. See "Clockrec Source Select" page for more details. Reserved. Always read as "00".
Table 222 - Pin Mux 0 Register
Address: 862h Label: pinmux_reg1 Reset Value: 0202h Label pinmux_recov_d_sel reserved pinmux_recov_c_sel reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description This field selects the recov_d output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00" This field selects the recov_c output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00"
Table 223 - Pin Mux 1 Register
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Address: 864h Label: pinmux_reg2 Reset Value: 0202h Label pinmux_recov_f_sel reserved pinmux_recov_e_sel reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description
Data Sheet
This field selects the recov_f output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00" This field selects the recov_e output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00"
Table 224 - Pin Mux 2 Register
Address: 866h Label: pinmux_reg3 Reset Value: 0202h Label pinmux_recov_h_sel reserved pinmux_recov_g_sel reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description This field selects the recov_h output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00" This field selects the recov_g output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00"
Table 225 - Pin Mux 3 Register
Address: 868h Label: pinmux_reg4 Reset Value: 0202h Label pinmux_ct_netref2_sel reserved pinmux_ct_netref1_sel reserved Bit Position 5:0 7:6 13:8 15:14 Type RW RO RW RO Description This field selects the ct_netref2 output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00" This field selects the ct_netref1 output. See Table 28 "Source Selection" on page 89 for more details. Reserved. Always read as "00"
Table 226 - Pin Mux 4 Register
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Address: 86Ah Label: pinmux_reg5 Reset Value: 0303h Label pinmux_local_netref_16m_sel Bit Position 5:0 Type RW Description
Data Sheet
This field selects the local_16m reference feed into the H.100 master circuit. See Table 28 - "Source Selection" on page 89 for more details. Reserved. Always read as "00" Reserved. Always read as "0000_00" Reserved. Always read as "00"
reserved reserved reserved
7:6 13:8 15:14
RO RO RO
Table 227 - Pin Mux 5 Register
Address: 880h Label: diviclk0_reg0 Reset Value: 0300h Label diviclk0_clk_divisor_load_now diviclk0_clk_divisor_reset diviclk0_even_duty_cycle_selec t diviclk0_input_invert_select diviclk0_output_invert_select reserved diviclk0_input_source_select Bit Position 0 1 2 3 4 12:7 13:8 Type PUL RW RW RW RW RW RW Description When this bit is written to '1', the integer clock divisor 0's division value will be loaded into the divisor. When this bit is '0', the integer clock divisor 0 is put in reset. Must be '1' for normal operation. When '1', the duty cycle modifier will be enabled and will generate a 50% duty cycle output. When '1', the input of the integer clock divisor will be inverted before being divided. When '1', the output of the integer clock divisor will be inverted before being sent out. Reserved. Must always be "0000_00" This field selects the input of the integer clock divisor. See Table 28 - "Source Selection" on page 89 for more details. Reserved. Must always be "00"
reserved
15:14
RW
Table 228 - Integer Clock Divisor0 0 Register
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Address: 882h Label: diviclk0_reg1 Reset Value: 0000h Label diviclk0_ext_loss_pulse Bit Position 0 Type ROLO Description
Data Sheet
This bit is set when an external signal indicates that the input of the integer clock divisor is invalid (such as a PHY alarm). Same as diviclk0_ext_loss_pulse, but when the error condition ceases, this bit will clear itself. This bit is set when the integer clock divisor input's frequency is off as compared to the expected frequency (received frequency is too high). Same as diviclk0_freq_too_high_pulse, but when the error condition ceases, this bit will clear itself. This bit is set when the integer clock divisor input's frequency is off as compared to the expected frequency (received frequency is too low). Same as diviclk0_freq_too_low_pulse, but when the error condition ceases, this bit will clear itself. Reserved. Always read as "0000_0000_00"
diviclk0_ext_loss_flag diviclk0_freq_too_high_pulse
1 2
RO ROLO
diviclk0_freq_too_high_flag diviclk0_freq_too_low_pulse
3 4
RO ROLO
diviclk0_freq_too_low_flag reserved
5 15:6
RO RO
Table 229 - Integer Clock Divisor0 1 Register
Address: 884h Label: diviclk0_reg2 Reset Value: 0000h Label diviclk0_ext_loss_pulse_ie reserved diviclk0_freq_too_high_pulse_ie reserved diviclk0_freq_too_low_pulse_ie reserved reserved Bit Position 0 1 2 3 4 5 15:6 Type IE RO IE RO IE RO RO Description When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "00" When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "00" When '1' and the corresponding status bit is '1', and interrupt will be generated. Reserved. Always read as "00" Reserved. Always read as "0000_0000_00"
Table 230 - Integer Clock Divisor0 2 Register
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Address: 886h Label: diviclk0_reg3 Reset Value: 0000h Label diviclk0_ext_loss_pulse_genloss diviclk0_ext_loss_flag_genloss diviclk0_freq_too_high_pulse_genloss diviclk0_freq_too_high_flag_genloss diviclk0_freq_too_low_pulse_genloss diviclk0_freq_too_low_flag_genloss reserved Bit Position 0 1 2 3 4 5 15:6 Type RW RW RW RW RW RW RW Description
Data Sheet
When set, the corresponding status will cause a loss to be signaled for this diviclk. When set, the corresponding status will cause a loss to be signaled for this diviclk. When set, the corresponding status will cause a loss to be signaled for this diviclk. When set, the corresponding status will cause a loss to be signaled for this diviclk. When set, the corresponding status will cause a loss to be signaled for this diviclk. When set, the corresponding status will cause a loss to be signaled for this diviclk. Reserved. Must always be "0000_0000_00"
Table 231 - Integer Clock Divisor0 3 Register
Address: 888h Label: diviclk0_reg4 Reset Value: 0063h Label diviclk0_ext_loss_source_select Bit Position 5:0 Type RW Description Select's which external pin will signal that the input of the integer clock divisor is good or not. See Table 28 - "Source Selection" on page 89 for more details. Input of the integer clock divisor is considered bad when the select ext_loss signal is active (i.e. equal to this bit). 0 = source loss active low; 1 = source loss active high. When a loss is detected, the output signal indicating this loss is activated (i.e. the value is this register is sent out). '0' = output loss active low; '1' = output loss active high. Reserved. Must always be "0000_0000"
diviclk0_ext_loss_source_polarity
6
RW
diviclk0_output_loss_polarity
7
RW
reserved
15:8
RW
Table 232 - Integer Clock Divisor0 4 Register
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Address: 88Ah Label: diviclk0_reg5 Reset Value: 0000h Label diviclk0_clk_div Bit Position 15:0 Type RW Description
Data Sheet
This is the denominator used to divide the input clock. It ranges from 1 to 65535.
Table 233 - Integer Clock Divisor0 5 Register
Address: 890h Label: diviclk0_reg8 Reset Value: 0000h Label diviclk0_freqchck_div Bit Position 15:0 Type RW Description This value will be used to divide the input clock before check it against the frequency of mclk. The higher the division value, the longer to detect a frequency too high or frequency too low, but the check is more precise. 0000h disables frequency checking.
Table 234 - Integer Clock Divisor0 8 Register
Address: 892h Label: diviclk0_reg9 Reset Value: 0000h Label diviclk0_freqchck_max_mclk_cycles Bit Position 15:0 Type RW Description This regsiter defines the maximum number of mclk cycles between two rising edges of the input clock divided by diviclk0_freqchck_div. If a second rising edge has not been detected in diviclk0_freqchck_max_mclk_cycles, the diviclk0_freq_too_low will be detected.
Table 235 - Integer Clock Divisor0 9 Register
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Address: 894h Label: diviclk0_reg10 Reset Value: 0000h Label diviclk0_freqchck_min_mclk_cycles Bit Position 15:0 Type RW Description
Data Sheet
This regsiter defines the minimum number of mclk cycles between two rising edges of the input clock divided by diviclk0_freqchck_div.If a second rising edge has been detected in less then diviclk0_freqchck_min_mclk_cycles, the diviclk0_freq_too_high will be detected.
Table 236 - Integer Clock Divisor0 10 Register
Address: 8A0h Label: diviclk1_reg0 Reset Value: 0300h Label diviclk1_clk_divisor_load_now diviclk1_clk_divisor_reset diviclk1_even_duty_cycle_select diviclk1_input_invert_select diviclk1_output_invert_select diviclk1_input_source_select reserved Bit Position 0 1 2 3 4 13:8 15:14 Type PUL RW RW RW RW RW RW Reserved. Must always be "00" Description See regsiters 880h to 89Eh
Table 237 - Integer Clock Divisor1 0 Register
Address: 8A2h Label: diviclk1_reg1 Reset Value: 0000h Label diviclk1_ext_loss_pulse diviclk1_ext_loss_flag diviclk1_freq_too_high_pulse diviclk1_freq_too_high_flag Bit Position 0 1 2 3 Type ROLO RO ROLO RO See register 882h. Description
Table 238 - Integer Clock Divisor1 1 Register
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Address: 8A2h Label: diviclk1_reg1 Reset Value: 0000h Label diviclk1_freq_too_low_pulse diviclk1_freq_too_low_flag reserved Bit Position 4 5 15:6 Type ROLO RO RO Description
Data Sheet
Reserved. Always read as "0000_0000_00"
Table 238 - Integer Clock Divisor1 1 Register
Address: 8A4h Label: diviclk1_reg2 Reset Value: 0000h Label diviclk1_ext_loss_pulse_ie reserved diviclk1_freq_too_high_pulse_ie reserved diviclk1_freq_too_low_pulse_ie reserved reserved Bit Position 0 1 2 3 4 5 15:6 Type IE RO IE RO IE RO RO Reserved. Always read as "0000_0000_00" See register 884h. Description
Table 239 - Integer Clock Divisor1 2 Register
Address: 8A6h Label: diviclk1_reg3 Reset Value: 0000h Label diviclk1_ext_loss_pulse_genloss diviclk1_ext_loss_flag_genloss diviclk1_freq_too_high_pulse_genloss diviclk1_freq_too_high_flag_genloss diviclk1_freq_too_low_pulse_genloss Bit Position 0 1 2 3 4 Type RW RW RW RW RW Description See register 886h.
Table 240 - Integer Clock Divisor1 3 Register
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Address: 8A6h Label: diviclk1_reg3 Reset Value: 0000h Label diviclk1_freq_too_low_flag_genloss reserved Bit Position 5 15:6 Type RW RW Description
Data Sheet
Reserved. Must always be "0000_0000_00"
Table 240 - Integer Clock Divisor1 3 Register (continued)
Address: 8A8h Label: diviclk1_reg4 Reset Value: 0063h Label diviclk1_ext_loss_source_select diviclk1_ext_loss_source_polarity diviclk1_output_loss_polarity reserved Bit Position 5:0 6 7 15:8 Type RW RW RW RW Reserved. Must always be "0000_0000" Description See register 888h.
Table 241 - Integer Clock Divisor1 4 Register
Address: 8AAh Label: diviclk1_reg5 Reset Value: 0000h Label diviclk1_clk_div Bit Position 15:0 Type RW See register 88Ah. Description
Table 242 - Integer Clock Divisor1 5 Register
Address: 8B0h Label: diviclk1_reg8 Reset Value: 0000h Label diviclk1_freqchck_div Bit Position 15:0 Type RW See register 890h. Description
Table 243 - Integer Clock Divisor1 8 Register
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Address: 8B2h Label: diviclk1_reg9 Reset Value: 0000h Label diviclk1_freqchck_max_mclk_cycles Bit Position 15:0 Type RW See register 892h. Description
Data Sheet
Table 244 - Integer Clock Divisor1 9 Register
Address: 8B4h Label: diviclk1_reg10 Reset Value: 0000h Label diviclk1_freqchck_min_mclk_cycles Bit Position 15:0 Type RW See register 894h. Description
Table 245 - Integer Clock Divisor1 10 Register
Address: 8C0h Label: diviclk2_reg0 Reset Value: 0300h Label diviclk2_clk_divisor_load_now diviclk2_clk_divisor_reset diviclk2_even_duty_cycle_select diviclk2_input_invert_select diviclk2_output_invert_select diviclk2_input_source_select reserved Bit Position 0 1 2 3 4 13:8 15:14 Type PUL RW RW RW RW RW RW Reserved. Must always be "00" Description See registers 880h to 89Eh
Table 246 - Integer Clock Divisor2 0 Register
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Address: 8C2h Label: diviclk2_reg1 Reset Value: 0000h Label diviclk2_ext_loss_pulse diviclk2_ext_loss_flag diviclk2_freq_too_high_pulse diviclk2_freq_too_high_flag diviclk2_freq_too_low_pulse diviclk2_freq_too_low_flag reserved Bit Position 0 1 2 3 4 5 15:6 Type ROLO RO ROLO RO ROLO RO RO See register 8A2h. Description
Data Sheet
Reserved. Always read as "0000_0000_00"
Table 247 - Integer Clock Divisor2 1 Register
Address: 8C4h Label: diviclk2_reg2 Reset Value: 0000h Label diviclk2_ext_loss_pulse_ie reserved diviclk2_freq_too_high_pulse_ie reserved diviclk2_freq_too_low_pulse_ie reserved reserved Bit Position 0 1 2 3 4 5 15:6 Type IE RO IE RO IE RO RO Reserved. Always read as "0000_0000_00" See register 8A4h. Description
Table 248 - Integer Clock Divisor2 2 Register
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Address: 8C6h Label: diviclk2_reg3 Reset Value: 0000h Label diviclk2_ext_loss_pulse_genloss diviclk2_ext_loss_flag_genloss diviclk2_freq_too_high_pulse_genloss diviclk2_freq_too_high_flag_genloss diviclk2_freq_too_low_pulse_genloss diviclk2_freq_too_low_flag_genloss reserved Bit Position 0 1 2 3 4 5 15:6 Type RW RW RW RW RW RW RW Description See register 8A6h.
Data Sheet
Reserved. Must always be "0000_0000_00"
Table 249 - Integer Clock Divisor2 3 Register
Address: 8C8h Label: diviclk2_reg4 Reset Value: 0063h Label diviclk2_ext_loss_source_select diviclk2_ext_loss_source_polarity diviclk2_output_loss_polarity reserved Bit Position 5:0 6 7 15:8 Type RW RW RW RW Reserved. Must always be "0000_0000" See register 8A8h. Description
Table 250 - Integer Clock Divisor2 4 Register
Address: 8CAh Label: diviclk2_reg5 Reset Value: 0001h Label diviclk2_clk_div Bit Position 15:0 Type RW See register 8AAh. Description
Table 251 - Integer Clock Divisor2 5 Register
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Address: 8D0h Label: diviclk2_reg8 Reset Value: 0000h Label diviclk2_freqchck_div Bit Position 15:0 Type RW See register 8B0h. Description
Data Sheet
Table 252 - Integer Clock Divisor2 8 Register
Address: 8D2h Label: diviclk2_reg9 Reset Value: 0000h Label diviclk2_freqchck_max_mclk_cycles Bit Position 15:0 Type RW See register 8B2h. Description
Table 253 - Integer Clock Divisor2 9 Register
Address: 8D4h Label: diviclk2_reg10 Reset Value: 0000h Label diviclk2_freqchck_min_mclk_cycles Bit Position 15:0 Type RW See register 8B4h. Description
Table 254 - Integer Clock Divisor2 10 Register
Address: 8E0h Label: tx_srts_debug Reset Value: 0000h Label tx_srts_eight_cell_pulse_rol tx_srts_fnxi_cnt reserved Bit Position 0 11:8 15:12 Type ROL RO RO Only used for tests. Only used for tests. Reserved. Always read as "0000" Description
Table 255 - TX SRTS Debug Register
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Address: 8E4h Label: adapsrts0_rx_srts_debug Reset Value: 0000h Label adapsrts0_eight_cell_pulse_rol adapsrts0_rx_srts_fnxi_cnt reserved Bit Position 0 11:8 15:12 Type ROL RO RO Only used for tests. Only used for tests. Reserved. Always read as "0000" Description
Data Sheet
Table 256 - RX SRTS Debug 0 Register
Address: 8E8h Label: adapsrts1_rx_srts_debug Reset Value: 0000h Label adapsrts1_eight_cell_pulse_rol adapsrts1_rx_srts_fnxi_cnt reserved Bit Position 0 11:8 15:12 Type ROL RO RO Only used for tests. Only used for tests. Reserved. Always read as "0000" Description
Table 257 - RX SRTS Debug 1 Register
Address: 8ECh Label: adapsrts_aal1_err_debug Reset Value: 0000h Label adapsrts0_valid_cell adapsrts0_cell_lost adapsrts1_valid_cell adapsrts1_cell_lost reserved Bit Position 0 1 2 3 15:4 Type ROL ROL ROL ROL ROL Only used for tests. Only used for tests. Only used for tests. Only used for tests. Reserved. Always read as "0000_0000_0000" Description
Table 258 - AAL1 Error Debug Register
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5.5.9 Miscellaneous Registers
Data Sheet
Address: 900h Label: control Reset Value: 0000h Label test_status Bit Position 15 Type TS Description When '1', all the status bits in the register will be set.
Table 259 - Miscellaneous Control Register
Address: 902h Label: err_reg0 Reset Value: 0000h Label adap_srts_remote0_mem_overflow Bit Position 0 Type ROL Description Indicates that the chip did not have time to write an adaptive point structure before the next one was generated. Indicates that the chip did not have time to write an adaptive point structure before the next one was generated. Indicates that the SRTS value buffer overflowed. Indicates that the SRTS value buffer overflowed. Indicates that the CAS change memory overflowed. New silent tones were requested before the current ones could be fetched. Reserved. Always read as "0000_0000_00"
adap_srts_remote1_mem_overflow
1
ROL
srts_local0_mem_overflow srts_local1_mem_overflow cas_mem_overflow silent_tone_error reserved
2 3 4 5 15:6 Table 260 -
ROL ROL ROL ROL ROL
Miscellaneous Error Register
Address: 908h Label: silent_tone_reg2 Reset Value: 0000h Label silent_size Bit Position 15:0 Type RW Description Size of the silent tone buffers, in bytes minus 1. 0 means 1 byte; FFFFh means 10000h bytes.
Table 261 - Silent Tone 2 Register
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Address: 90Ah Label: silent_tone_reg3 Reset Value: 0000h Label silent_base_add_15_0 Bit Position 15:0 Type RW Description
Data Sheet
The base address of the silent tone buffers (in words).
Table 262 - Silent Tone 3 Register
Address: 90Ch Label: silent_tone_reg3 Reset Value: 0000h Label silent_base_add_18_16 reserved Bit Position 2:0 15:3 Type RW RW Description The base address of the silent tone buffers (in words). Reserved. Must always be "0000_0000_0000_0"
Table 263 - Silent Tone 4 Register
Address: 90Eh Label: as0_srts_reg0 Reset Value: 0000h Label adap_srts0_size Bit Position 15:0 Type RW Description Size of the adaptive point/SRTS value buffer minus one. 0 means 1; FFFFh means 10000h.
Table 264 - Adaptive Point/SRTS Value 0 Register
Address: 910h Label: as0_srts_reg1 Reset Value: 0000h Label adap_srts0_base_add_15_0 Bit Position 15:0 Type RW Description The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored.
Table 265 - Adaptive Point/SRTS Base Address Low 0 Register
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Address: 912h Label: as0_srts_reg2 Reset Value: 0000h Label adap_srts0_base_add_18_16 Bit Position 2:0 Type RW Description
Data Sheet
The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. Reserved. Must always be "0000_0000_0000_0"
reserved
15:3
RW
Table 266 - Adaptive Point/SRTS Base Address High 0 Register
Address: 914h Label: as0_srts_reg3 Reset Value: 0000h Label adap_srts_remote0_write_pnt Bit Position 15:0 Type RO Description The chip's write pointer to the adaptive point/SRTS value buffer.
Table 267 - Adaptive Point/SRTS Write Pointer 0 Register
Address: 916h Label: as0_srts_reg4 Reset Value: 0000h Label adap_srts_remote0_read_pnt Bit Position 15:0 Type RW Description The CPU's read pointer to the adaptive point/SRTS value buffer.
Table 268 - Adaptive Point/SRTS Read Pointer 0 Register
Address: 918h Label: as0_srts_reg5 Reset Value: 0000h Label srts_local0_write_pnt Bit Position 15:0 Type RO Description The chip's write pointer to the local SRTS value buffer.
Table 269 - Local SRTS Write Pointer 0 Register
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Address: 91Ah Label: as0_srts_reg6 Reset Value: 0000h Label srts_local0_read_pnt Bit Position 15:0 Type RW Description
Data Sheet
The CPU's read pointer to the local SRTS value buffer.
Table 270 - Local SRTS Read Pointer 0 Register
Address: 91Ch Label: as1_srts_reg0 Reset Value: 0000h Label adap_srts1_size Bit Position 15:0 Type RW Description Size of the adaptive point/SRTS value buffer minus one. 0 means 1; FFFFh means 10000h.
Table 271 - Adaptive Point/SRTS Value 1 Register
Address: 91Eh Label: as1_srts_reg1 Reset Value: 0000h Label adap_srts1_base_add_15_0 Bit Position 15:0 Type RW Description The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored.
Table 272 - Adaptive Point/SRTS Base Address Low 1 Register
Address: 920h Label: as1_srts_reg2 Reset Value: 0000h Label adap_srts1_base_add_18_16 Bit Position 2:0 Type RW Description The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. Reserved. Must always be "0000_0000_0000_0"
reserved
15:3
RW
Table 273 - Adaptive Point/SRTS Base Address High 1 Register
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Address: 922h Label: as1_srts_reg3 Reset Value: 0000h Label adap_srts_remote1_write_pnt Bit Position 15:0 Type RO Description
Data Sheet
The chip's write pointer to the adaptive point/SRTS value buffer.
Table 274 - Adaptive Point/SRTS Write Pointer 1 Register
Address: 924h Label: as1_srts_reg4 Reset Value: 0000h Label adap_srts_remote1_read_pnt Bit Position 15:0 Type RW Description The CPU's read pointer to the adaptive point/SRTS value buffer.
Table 275 - Adaptive Point/SRTS Read Pointer 1 Register
Address: 926h Label: as1_srts_reg5 Reset Value: 0000h Label srts_local1_write_pnt Bit Position 15:0 Type RO Description The chip's write pointer to the local SRTS value buffer.
Table 276 - Local SRTS Write Pointer 1 Register
Address: 928h Label: as1_srts_reg6 Reset Value: 0000h Label srts_local1_read_pnt Bit Position 15:0 Type RW Description The CPU's read pointer to the local SRTS value buffer.
Table 277 - Local SRTS Read Pointer 1 Register
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Address: 92Ah Label: cas_reg0 Reset Value: 0000h Label cas_size Bit Position 15:0 Type RW Description
Data Sheet
Size of the CAS change buffer minus 1. 0 means 1; FFFFh means 10000h.
Table 278 - CAS Change Buffer Size Register
Address: 92Ch Label: cas_reg1 Reset Value: 0000h Label cas_base_add_15_0 Bit Position 15:0 Type RW Description Base address of the CAS change buffer.
Table 279 - CAS Change Buffer Base Address Low Register
Address: 92Eh Label: cas_reg2 Reset Value: 0000h Label cas_base_add_18_16 reserved Bit Position 2:0 15:3 Type RW RW Description Base address of the CAS change buffer. Reserved. Must always be "0000_0000_0000_0"
Table 280 - CAS Change Buffer Base Address High Register
Address: 930h Label: cas_reg3 Reset Value: 0000h Label cas_write_pnt Bit Position 15:0 Type RO Description The chip's write pointer to the CAS change buffer.
Table 281 - CAS Write Pointer Register
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Address: 932h Label: cas_reg4 Reset Value: 0000h Label cas_read_pnt Bit Position 15:0 Type RW Description The CPU's read pointer to the CAS change buffer.
Data Sheet
Table 282 - CAS Read Pointer Register
Address: 944h Label: cas_timeout_hig Reset Value: 0000h Label cas_timeout_period[19:16] reserved Bit Position 3:0 15:4 Type RW RW Description Time, in us, that a CAS change report can wait in the FIFO before an alarm is generated. Reserved. Must always be "0000_0000_0000"
Table 283 - CAS Timeout High Register
Address: 946h Label: cas_timeout_low Reset Value: 0000h Label cas_timeout_period[15:0] Bit Position 15:0 Type RW Description Time, in us, that a CAS change report can wait in the FIFO before an alarm is generated.
Table 284 - CAS Timeout Low Register
Address: 948h Label: treated pulses Reset Value: 0000h Label cas_treated_pulse Bit Position 0 Type PUL Description Written to '1' to indicate that CAS change FIFO has been treated. Another alarm will not be generated until the above timeout has elapsed. Reserved. Always read as "0000_0000_0000_000"
reserved
15:1
PUL
Table 285 - Treated Pulses Register
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Zarlink Semiconductor Inc.
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5.5.10 H.100 Registers
Data Sheet
Address: A00h Label: control0 Reset Value: 0000h Label h100_pll_ref_fallback Bit Position 0 Type RW Description '0' = always use selected external clk (selected by h100_pll_ext_source) to source pll's ref input. '1' = if selected clock fails, fallback on local 16.384mHz clock. '0' = source ct_c8_a_in. '1' = source ct_c8_b_in '0' = source pll's ref input with local 16.384mHz clock, '1' = source with selected external clk (selected via h100_pll_ext_source). '0' = use embedded PLL to generate outgoing clocks. '1' = bypass PLL and use local 16.384 mHz clock instead. '1' = loops the ct_c8 A and B clocks and frames back into the chip. Used for tests "00" = 2.048 mHz. "01" = 4.096 mHz. "10" = 8.192 mHz. '0' = tri-states ct_c8_a and ct_frame_a '0' = tri-states ct_c8_b and ct_frame_b '0' = tri-states all the compatibility signals Selects pll's fb input: "00" = sample A, "10" = sample B, "01" = sample PLL output (div 4), "11" = reserved. '0' = sync frame on ct_frame_a_in, '1' = sync frame on ct_frame_b_in specifies which clk to send to tdmint: '0' = use ct_c8_a. '1' = use ct_c8_b. h100_tdmint_clk_fallback can send other clk instead. clk to tdmint if selected clk is bad: '0' = always sync on selected clk (h100_tdming_clk_sel). '1' = if selected clk fails, switch over to backup clk. When '1', all the status bits in the register will be set.
h100_pll_ext_source h100_pll_local_source
1 2
RW RW
h100_pll_override h100_clk_loopback h100_sclk_speed h100_c8_frame_a_oe h100_c8_frame_b_oe h100_comp_oe h100_pll_fb_input h100_frame_sync_sourc e h100_tdmint_clk_sel
3 4 6:5 7 8 9 11:10 12 13
RW RW RW RW RW RW RW RW RW
h100_tdmint_clk_fallbac k test_status
14
RW
15
TS
Table 286 - H.100 Control 0 Register
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Zarlink Semiconductor Inc.
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Address: A02h Label: control1 Reset Value: 0000h Label h100_force_frame_sync_local Bit Position 0 Type RW Description
Data Sheet
Only applies if h100_pll_override is '0': '0' = sync frame on selected external frame (h100_frame_sync_source), '1' = sync frame on local 16.384 MHz clk. Reserved. Must always be "0000_0000_0000_000"
reserved
15:1
RW
Table 287 - H.100 Control 1 Register
Address: A04h Label: control2 Reset Value: 0000h Label h100_min_mclk_ct_c8 Bit Position 3:0 Type RW Description Minimum number of mclk cycles between ct_c8 rising edges, typically set using this equation: ((122 - 35) / mclk_period_ns) - 2. Maximum number of mclk cycles between ct_c8 rising edges, typically set using this equation: ((122 + 35) / mclk_period_ns) + 2. Reserved. Must always be "0000_000"
h100_max_mclk_ct_c8
8:4
RW
reserved
15:9
RW
Table 288 - H.100 Control 2 Register
Address: A08h Label: flags Reset Value: 0000h Label h100_clk_a_bad_latched Bit Position 0 Type RO Description Indicates that the ct_c8_a period is not within +/- 35 ns of what is was supposed to be. This is a RO signal, so it means that the error is currently occurring. Indicates that the ct_c8_b period is not within +/- 35 ns of what is was supposed to be. This is a RO signal, so it means that the error is currently occurring.
h100_clk_b_bad_latched
1
RO
Table 289 - H.100 Flags Register
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Address: A08h Label: flags Reset Value: 0000h Label h100_frame_a_bad_latched Bit Position 2 Type RO Description
Data Sheet
Indicates that the ct_frame_a is not occurring every 1024 ct_c8_a cycles. This is a RO signal, so it means that the error is currently occurring. Indicates that the ct_frame_b is not occurring every 1024 ct_c8_a cycles. This is a RO signal, so it means that the error is currently occurring. Reserved. Always read as "0000_0000_0000"
h100_frame_b_bad_latched
3
RO
reserved
15:4
RO
Table 289 - H.100 Flags Register (continued)
Address: A0Ah Label: status Reset Value: 0000h Label h100_clk_a_bad_rol Bit Position 0 Type ROLO Description Indicates that the ct_c8_a period is not within +/- 35 ns of what is was supposed to be. This is a ROL signal, so it means that the error has occurred since the last time this bit was cleared. Indicates that the ct_c8_b period is not within +/- 35 ns of what is was supposed to be. This is a ROL signal, so it means that the error has occurred since the last time this bit was cleared. Indicates that the ct_frame_a is not occurring every 1024 ct_c8_a cycles. This is a ROL signal, so it means that the error has occurred since the last time this bit was cleared. Indicates that the ct_frame_b is not occurring every 1024 ct_c8_a cycles. This is a ROL signal, so it means that the error has occurred since the last time this bit was cleared. Reserved. Always read as "0000_0000_0000"
h100_clk_b_bad_rol
1
ROLO
h100_frame_a_bad_rol
2
ROLO
h100_frame_b_bad_rol
3
ROLO
reserved
15:4
ROLO
Table 290 - H.100 Status Register
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Address: A0Ch Label: status_ie Reset Value: 0000h Label h100_clk_a_bad_rol h100_clk_b_bad_rol h100_frame_a_bad_rol h100_frame_b_bad_rol reserved Bit Position 0 1 2 3 15:4 Type IE IE IE IE IE Description
Data Sheet
When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as "0000_0000_0000"
Table 291 - H.100 Interrupt Enable Register
6.0
6.1
Statistics
TDM statistics
Underrun counter: 16-bit counter that counts the number of underruns detected by TDM interface.
6.2
TX SAR statistics
Percentage of bandwidth utilisation: a register (0510h) which indicates how many mclk cycles were required to treat the last frame. Transmitted Cell Counter: 32-bit counter that counts the number of cells transmitted on a particular VC. Each VC has its own counter in its structure.
6.3
RX SAR statistics
Error reporting structures allow software-based counters for the following errors: * * * * * * * * * * * P-byte absent error P-byte framing error P-byte range error P-byte parity error Overrun error Underrun error AAL1 CRC error AAL1 parity error Single cell loss Multiple cell loss Cell misinsertion
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Data Sheet
Received Cell Counter: 32-bit counter that counts the number of cells received on a particular VC. Each VC has its own counter in its structure.
6.4
UTOPIA statistics
Transmitted Cell Counters: 32-bit counters that counts the number of cells transmitted on a particular UTOPIA port. Three counters are available for each ports. Received Cell Counters: 32-bit counters that counts the number of cells received on a particular UTOPIA port. Each port has a dedicated counter. Cell loss counter: 16-bit counters that counts the number of cells lost in the UTOPIA module.
7.0
Programming the fast_clk PLL
The frequency received on mclk_src pin is used by the MT90503's PLL to generate a much higher frequency (fast_clk). It is then divided down to the output mem_clk frequency. The X, Y and Z divider can be programmed to be any value as defined in Table 292 and Table 293 on page 206. The MT90503 can support mclk_src with a frequency ranging from 30 MHz to 80 MHz. Only frequencies between 50 MHz and 53.3 MHz are not supported by the PLL. The X and Y divisor indicate what values can be programmed in the pll_conf registers 128h. Table 293, "Z Divisor Table," on page 206 indicates the range of output mem_clk that can be achieved. Note that the output mem_clk cannot be programmed to be above 80 MHz, or below 40 MHz. The fast_clk PLL drives the output mem_clk pins. These pins provide both TTL and PECL interfaces for the output mem_clk. For both types, the output pins for the mem_clk is always driven. However, when the output pins are not being used, the register bits that control the toggling of these two pins should be disabled to reduce power consumption. The user must configure the MT90503 to select the desired input mem_clk type, i.e., either PECL or TTL. The input mem_clk serves as the main clock (mclk) for the MT90503 and must be present for the MT90503 to function. It is absolutely necessary for the input mem_clk to be present and one of the inputs to be selected. The output mem_clk, however, are convenience for the user and do not have to be connected. These outputs eliminate the need for a second, high-speed oscillator to drive the input mem_clk. The clock that is connected to the mem_clk inputs on the MT90503, whether it is the TTL or PECL, must be in phase with the clock connected to SSRAM used with the chip. The maximum skew allowed is 0.5 ns.
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_ p _ Divide by Y FB
Data Sheet
Clock Multiplication PLL OUT fast_clk
mclk_src upclk
Divide by X
REF
Divide by Z
50 ohm Controled Impedance Output Buffer (3.3 V LVTTL) mem_clk_o
mem_clk_positive_o mem_clk_negative_o PECL Output Buffer
Figure 50 - mem_clk Output and fast_clk Generation Circuits
mem_clk_i 3.3 V LVTTL Input mclk PECL Input Buffer mclk Distribution Buffer + mem_clk_positive_i mem_clk_negative_i
Figure 51 - mem_clk Input and mclk Generation Circuit
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Div X 1 1 1 1 2 1 Div Y 6 5 4 3 5 2 mclk_src (MHz) 0 to 30 30 to 33.33 33.33 to 40 40 to 50 50 to 53.33 53.33 to 66.66 66.66 to 80 80 fast_clk (MHz) 180 to 200 166.66 to 200 160 to 200 160 to 200 166.66 to 200 160 to 200
Data Sheet
Table 292 - Register 0128h Frequency Values
Div Z 2 3 4
output mem_clk 80 53.3 to 66.6 40 to 50
Table 293 - Z Divisor Table
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8.0
8.1
Data Sheet
Electrical Specifications
DC Characteristics
Absolute Maximum Ratings Parameter 1 2 3 4 5 Supply Voltage - 3.3 Volt Rail Voltage on 3.3V Input pins Continuous current at digital inputs Continuous current at digital outputs Storage Temperature Symbol VDD VI II IO TS -40.0 Min. -0.3 -1.0 Max. 3.9 3.6 4.0 5.3 +85.0 Units V V mA mA C
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated. Long-term exposure to absolute maximum ratings may affect device reliability, and permanent damage may occur if operate exceeding the rating. The device should be operated under recommended operating condition.
Recommended Operating Conditions Characteristics 1 Operating Temperature Symbol TOP Min. -40.0 Typ. 25.0 Max. +85.0 Units C Test Conditions 2048 Channels with heat sink Note 1. 2048 Channels with no heat sink 1024 Channels with no heat sink
2 3 4 5
Operating Temperature Operating Temperature Supply Voltage, 3.3 Volt Rail Input Voltage - 3.3 V inputs
TOP TOP VDD VI
-40.0 -40.0 3.0 Vss-0.5
25.0 25.0 3.3 3.3
+70.0 +85.0 3.6 VDD+0.3
C C V V
Note 1: Suitable heat sinks: Part Number 66435, Avvid Thermalloy and Part Number HS2141, Intricast, or other similar heat sinks. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
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DC Characteristics Characteristics 1 Supply Current - 3.3 V supply Symbol IDD Min. Typ. 720.0 Max. Units mA
Data Sheet
Test Conditions 50.0 MHz, Nominal output loads, 1024 Channels, 16 streams active. 80.0 MHz, Nominal output loads, 2048 Channels 50.0 MHz, Nominal output loads, 1024 Channels, 16 streams active. 80.0 MHz, Nominal output loads, 2048 Channels
2
Supply Current - 3.3 V supply
IDDN
970.0
mA
3
Device Power Dissipation
PDD1
2.38
W
4
Device Power Dissipation
PDD2
3.2
W
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Input High Voltage Input Low Voltage Switching Threshold Schmitt Trigger Positive Threshold Schmitt Trigger Neg. Threshold Input Leakage Current Input Pin Capacitance Output Pin Capacitance Output High Impedance Leakage Output HIGH Voltage Output LOW Voltage 3.3V output HIGH current (4 mA buffer) 3.3V output LOW current (4 mA buffer) 3.3V output HIGH current (8 mA buffer) 3.3V output LOW current (8 mA buffer) 3.3V output HIGH current (12 mA buffer)
VIH VIL VTC Vt+ VtII CI CO IOZ VOH VOL IOH IOL IOH IOL IOH
2.0 Vss-0.5 1.4 1.7 0.8 -10.0 2.5 2.0 -10.0 2.4 0.2 +/- 1.0
VDD+0 .3 0.8 2.0 2.0 1.0 10.0
V V V V V A pF pF VIN = VDDx or Vss
10.0 VDD 0.4 4.0 4.0 8.0 8.0 12.0
A V V mA mA mA mA mA
VO = VSS or VDD IOH = rated current IOL = rated current VOH = 2.4 V VOL = 0.4 V VOH = 2.4 V VOL = 0.4 V VOH = 2.4 V
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DC Characteristics (continued) 21 22 3.3V output LOW current (12 mA buffer) Junction-to-Ambient Thermal Resistance IOL 12.0 14.225 mA C/W
Data Sheet
VOL = 0.4 V 0 cfm air flow (natural convection airflow only)
J-A
b. TOP = 0C to 70C; VDD = 3.3V 5% Voltage measurements are with respect to ground (V SS) unless otherwise stated.
8.1.1
Precautions During Power Sequencing
Latch-up is not a concern during power sequencing. The only requirement for sequencing 3.3 V and 5 V supplies during power up is that the MT90503 be either held in reset until the rails are stable or have its global_tri_state pin held low (tristate). However, to minimise over-voltage stress during system start-up, the 3.3 V supply applied to the MT90503 should be brought to a level of at least VDD = 3.0 V before a signal line is driven to a level greater than or equal to 3.3 V. This practice can be implemented either by ensuring that the 3.3 V power turns on simultaneously with or before the system 5 V supply turns on, or by ensuring that all 5 V signals are held to a logic LOW state during the time that VDD < 3.0 V. This condition is also met also if the MT90503 is held in reset until VDD reaches 3.0 V. Regardless of the method chosen to limit over-voltage stress during power up, exposure must be limited to no more than + 6.5 V input voltage (VIN). The global_tri_state pin of the MT90503 can be asserted low on power-up to prevent bus contention.
8.1.2
Precautions During Power Failure
Latch-up is not a concern in power failure mode. Although extended exposure of the MT90503 to 5 V signals during 3.3 V supply power failure is not recommended, there are no restrictions as long as VIN does not exceed the absolute maximum rating of 6.5 V. To minimise over-voltage stress during a 3.3 V power supply failure, the designer should either link the power supplies to prevent this condition or ensure that all 5 V signals connected to the MT90503 are held in a logic LOW state until the 5 V supply is deactivated.
8.1.3
Pull-ups
Pull-ups from the 5 V rail to 3.3 V (5 V tolerant) outputs of the MT90503 can cause reverse leakage currents into those 3.3V outputs when they are active HIGH. (No significant reverse current is present during the high impedance state.) If the application can put the MT90503 in a state where MCLK is stopped, and a large number of 3.3 V output buffers are held in a static HIGH state, current can flow from the 5 V rail to the 3.3 V rail. If this MCLK-stopped state can not be avoided, the user should determine if the total MT90503 reverse current will have a negative impact on the system 3.3 V power supply. Alternatively, the global_tri_state pin of the MT90503 can be asserted low to put all outputs in the high impedance state.
8.2
H.110 Diode Clamp Rail
As the MT90503 has a diode clamp to the 5 V rail, the diode clamp must be no more than 0.7 V below VDD when the pin is not tristated. This can be accomplished by asserting the global_tri_state pin low or by keeping the MT90503 in reset until all rails are stable.
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8.3 AC Characteristics
Data Sheet
All pins are tested with 50 pf worst case loading and 15 pf best case loading unless otherwise specified. Minimum Frequency 40 MHz 30 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 8.192 MHz 8.192 MHz 0 MHz 0 MHz 0 MHz 0 MHz 0 MHz 0 MHz 0 MHz 0 MHz Maximum Frequency 80 MHz 80 MHz 50 MHz 50 MHz 50 MHz 50 MHz 50 MHz 50 MHz 65.536 MHz 8.192 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz Required For Device Operation Yes Yes No No No No No No No No No No No No No No No No Minimum Duty Cycle 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% 40% Maximum Duty Cycle 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60% 60%
Clock Name mem_clk_i mclk_src rxa_clk rxb_clk rxc_clk txa_clk txb_clk txc_clk pll_clk ct_c8_a/b recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h
Table 294 - Clock Networks
Characteristic mem_clk_i Frequency mem_clk_i Pulse Width (HIGH / LOW)
Sym tMF tMH/L
Min 40.0 5.0
Typ 80.0 6.25
Max 80.0 7.5
Unit s MHz ns
Test Conditions 30ppm clock recommended for TDM PLLs For 80MHz operation.
Table 295 - MCLK - Master Clock Input Parameters
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Zarlink Semiconductor Inc.
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9.0
9.1
Data Sheet
Interface Timing
CPU Interface Timing
write_active t4 inmo_rdy inmo_a[14:0] /inmo_das inmo_d[15:0] t1 Address Valid t1 Data Valid t3 t3 t5 t2 t6
Note: write_active = (inmo_cs = 0) AND (inmo_wr = 0)
Figure 52 - Non-multiplexed CPU Write Access - Intel Mode
read_active t4 inmo_rdy inmo_a[14:0] /inmo_das inmo_d[15:0] Note: read_active = (inmo_cs = 0) AND (inmo_rd = 0) t1 Address Valid t8 t7 Data Valid t3 t5 t2 t6
Figure 53 - Non-multiplexed CPU Read Access - Intel Mode
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Symbol t1 t2 t3 t4 t5 t6 Symbol t1 t2 t3 t4 t5 t6 t7 t8 Description Write Access write_access_active falling to inmo_d/inmo_a_das/inmo_a valid inmo_rdy_ndtack rising to write_access_active rising inmo_rdy_ndtack rising to inmo_d/inmo_a_das/inmo_a invalid write_access_active falling to inmo_rdy_ndtack falling Write Access Time write_access_active rising to inmo_rdy_ndtack tri-state Description Read Access read_access_active falling to inmo_a_das/inmo_a valid inmo_rdy_ndtack rising to read_access_active rising inmo_rdy_ndtack rising to inmo_a_das/inmo_a invalid read_access_active falling to inmo_rdy_ndtack falling Read Access Time read_access_active rising to inmo_rdy_ndtack tri-state inmo_d valid to inmo_rdy_ndtack rising read_access_active falling to inmo_d driving 0 mclk_src - 4 3*mclk_src -4 0 0 0 12 0 Min. Typ. 0 0 0 12 740 10 Max. Min. Typ. Max.
Data Sheet
Unit ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns
2*mclk_src - 4
2*mclk_src - 4
See Table 300 10
Table 296 - Non-multiplexed CPU Interface Intel Mode
write_active inmo_ale
t1 t8 t9
t2
t10 Data Valid t5
t4
inmo_d[15:0] t7 inmo_rdy
Address Valid
t3
t6
Note: write_active = (inmo_cs = 0) AND (inmo_wr = 0)
Figure 54 - Multiplexed CPU Write Access - Intel Mode
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Data Sheet
read_active inmo_ale t10 inmo_d[15:0] t4 inmo_rdy
t1 t7
t8
t11
Address Valid
t9
t3
Data Valid t5 t2 t6
Note: read_active = (inmo_cs = 0) AND (inmo_rd = 0)
Figure 55 - Multiplexed CPU Read Access - Intel Mode
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Symbol t1 t2 t3 t4 t5
Description Write Access write_access_active falling to inmo_ale falling write_access_active falling to inmo_d valid (writes) inmo_rdy_ndtack rising to write_access_active rising inmo_rdy_ndtack rising to inmo_ale rising & inmo_d invalid Write Access Time write_access_active rising to inmo_rdy_ndtack tri-state write_access_active falling to inmo_rdy_ndtack falling inmo_ale high pulse width inmo_d valid to inmo_ale falling inmo_ale falling to inmo_d invalid Description Read Access read_access_active falling to inmo_ale falling inmo_rdy_ndtack rising to read_access_active rising inmo_rdy_ndtack rising to inmo_ale rising read_access_active falling to inmo_rdy_ndtack falling Read Access Time
Min.
Typ.
Max. 2*mclk_src - 4 2*mclk_src - 4
Unit ns ns ns ns
0 0 740 0 0 5 5 0 Min. 0 0 0 12 See Table 300 Typ. Max. 2*mclk_src - 4 10 12
ns ns ns ns ns ns Unit ns ns ns ns ns
Table 297 - Multiplexed CPU Interface Intel Mode
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t6 t7 t8 t9 t10 t11 read_access_active rising to inmo_rdy_ndtack tri-state inmo_ale high pulse width read_access_active falling to inmo_d driving inmo_d valid to inmo_rdy_ndtack falling inmo_d valid to inmo_ale falling inmo_ale falling to inmo_d invalid 0 5 3*mclk_src 4 mclk_src - 4 5 0 10
Data Sheet
ns ns ns ns ns ns
Table 297 - Multiplexed CPU Interface Intel Mode (continued)
Figure 56 - Non-Multiplexed CPU Interface Write Access - Motorola Mode
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Data Sheet
Figure 57 - Non-multiplexed CPU Interface Read Access - Motorola Mode
Symbol t1
Description Write Access Address & Data Setup -- inmo_cs and inmo_rd_ds asserted to inmo_a[14:0] and inmo_d[15:0] and inmo_a_das valid Address & Data Hold -- inmo_rdy_ndtack low to inmo_a[14:0[ and inmo_d[15:0] and inmo_a_das invalid Inmo_rdy_ndtack high -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving one Inmo_rdy_ndtack delay -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving zero Inmo_rdy_ndtack hold -- inmo_cs and inmo_rd_ds de-asserted to inmo_rdy_ndtack drivingb one Inmo_rdy_ndtack high impedance -inmo_rdy_ndtack driving one to inmo_rdy_ndtack high impedance R/W setup -- R/W asserted to inmo_cs asserted R/W hold -- inmo_cs deasserted to R/W deasserted
Min.
Typ.
Max. 2*mclk_src - 4
Unit ns
t3
0
ns
t4 t5 t6 t7
0
12 740
ns ns ns ns
0 2
10 8
t11 t12
0 0
ns ns
Note: t1, t4, and t5 are dependent upon the last of inmo_cs and inmo_rd_ds to be asserted. t6 is dependent on the first of inmo_cs and inmo_rd_ds to be de-asserted. Symbol t1 Description Read Access Address Setup -- inmo_cs and inmo_rd_ds asserted to inmo_a[14:0[ and inmo_a_das valid Min. Typ. Max. 2*mclk_src - 4 Unit ns
Table 298 - Non-multiplexed CPU Interface Motorola Mode
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Symbol t3 t4 t5 t6 t7 Description Write Access Address Hold -- inmo_rdy_ndtack low to inmo_a[14:0] and inmo_a_das invalid Inmo_rdy_ndtack high -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving one Inmo_rdy_ndtack delay -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack asserted Inmo_rdy_ndtack hold -- inmo_cs or inmo_rd_ds de-asserted to inmo_rdy_ndtack driving one Inmo_rdy_ndtack high impedance -inmo_rdy_ndtack driving one to inmo_rdy_ndtack high-impedance Data to inmo_rdy_ndtack delay -- inmo_d[15:0] valid to inmo_rdy_ndtack asserted Data output hold -- inmo_cs or inmo_rd_ds de-asserted to inmo_d[15:0] invalid R/W setup -- R/W asserted to inmo_cs asserted R/W hold -- inmo_cs deasserted to R/W deasserted 0 2 Min. 0 0 12 Typ. Max.
Data Sheet
Unit ns ns ns ns ns
See Table 300 10 8
t9 t10 t11 t12
mclk_src - 4 0 0 0 10
ns ns ns ns
Note: t1, t4, and t5 are dependent upon the last of inmo_cs and inmo_rd_ds to be asserted. t6, and t10 are dependent on the first of inmo_cs and inmo_rd_ds to be de-asserted.
Table 298 - Non-multiplexed CPU Interface Motorola Mode (continued)
write_active inmo_ale t10 inmo_d[15:0] t9 inmo_rdy
t1 t8
t2
t11
Address Valid
t4 Data Valid t5 t3 t6 t7
Notes: write_active = (inmo_cs = 0) AND (inmo_ds = 0) AND (inmo_r/w = 0)
Figure 58 - Multiplexed CPU Interface Write Access - Motorola Mode
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Data Sheet
read_active inmo_ale t12 inmo_d[15:0] t4 inmo_rdy
t1 t11
t8
t13
Address Valid
t9
t3 Data Valid
t10 t6 t7
t5
t2
Notes: read_active = (inmo_cs = 0) AND (inmo_ds = 0) AND (inmo_r/w = 1)
Figure 59 - Multiplexed CPU Interface Read Access - Motorola Mode
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Symbol t1 t2 t3 t4
Description Write Access write_access_active falling to inmo_ale falling write_access_active falling to inmo_d valid (writes) inmo_rdy_ndtack falling to write_access_active rising inmo_rdy_ndtack falling to inmo_ale rising & inmo_d invalid Write Access Time write_access_active rising to inmo_rdy_ndtack rising inmo_rdy_ndtack rising to inmo_rdy_ndtack tri-state inmo_ale high pulse width write_access_active falling to inmo_rdy_ndtack driven high inmo_d valid to inmo_ale falling inmo_ale falling to inmo_d invalid Description Read Access read_access_active falling to inmo_ale falling inmo_rdy_ndtack falling to read_access_active rising inmo_rdy_ndtack falling to inmo_ale rising read_access_active falling to inmo_rdy_ndtack driving high
Min.
Typ.
Max. 2*mclk_src - 4 2*mclk_src - 4
Unit ns ns ns ns
0 0 740 0 2 5 0 5 0 Min 0 0 0 12 Typ Max 2*mclk_src - 4 12 10 8
ns ns ns ns ns ns ns Unit ns ns ns ns
Table 299 - Multiplexed CPU Interface Motorola Mode
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Symbol t5 t6 t7 t8 t9 t10 t11 t12 t13 Description Write Access Read Access Time read_access_active rising to inmo_rdy_ndtack rising inmo_rdy_ndtack rising to inmo_rdy_ndtack tri-state read_access_active falling to inmo_d driving inmo_d valid to inmo_rdy_ndtack falling read_access_active rising to inmo_d tri-state inmo_ale high pulse width inmo_d valid to inmo_ale falling inmo_ale falling to inmo_d invalid 0 2 3*mclk_src 4 mclk_src - 4 0 5 5 0 10 Min. Typ. Max.
Data Sheet
Unit ns ns ns ns ns ns ns ns ns
See Table 300 10 8
Table 299 - Multiplexed CPU Interface Motorola Mode (continued)
Symbol t5 t5 t5 t5
Description register and internal memory access SSRAM SSRAM SSRAM
Burst Length 1 word 1 word 8 words 128 words
Max. 740 1.07 1.44 8.78
Unit ns s s s
Table 300 - t5 Read Access Time
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9.2 UTOPIA Interface Timing
Data Sheet
t1 {tx,rx}{a,b,c}_clk
t2
inputs*
outputs** t5 t3 t4 t6
ATM Mode: * includes signals: {tx,rx}{a,b,c}_clav, rx{a,b,c}_soc, rx{a,b,c}_d[], rx{a,b,c}_par ** includes signals: {tx,rx}{a,b,c}_enb, tx{a,b,c}_soc, tx{a,b,c}_d[ ], tx{a,b,c}_par PHY Mode: * includes signals: {tx,rx}{a,b,c}_enb, rx{a,b,c}_soc, rx{a,b,c}_d[], rx{a,b,c}_par, {tx,rx}a_addr[ ] ** includes signals: {tx,rx}{a,b,c}_clav, tx{a,b,c}_soc, tx{a,b,c}_d[ ], tx{a,b,c}_par
Figure 60 - UTOPIA Timing
Characteristics 1 2 3 4 5 6 Input setup time Input hold time Clock to data valid Clock to data change Clock rising to signal driven Clock rising to signal tri-state
Symbol t1 t2 t3 t4 t5 t6
Min. 4 1
Max.
Units ns ns
12 2 1 1 20
ns ns ns ns
Table 301 - UTOPIA Bus Timing
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9.3 External Memory Timing
0ns mem_clk t3 mem_cs t3 mem_rw t3 mem_a t3 mem_bws "11" "00" t3 t5 mem_d
data valid
address valid
Data Sheet
10ns
20ns
30ns
40ns
5
t4
t4
t4
t4 "11" t6 t4 data valid t4 t6 parity valid
t3 t5 mem_par
Figure 61 - Flowthrough ZBT External Memory Timing - Write Access
0ns mem_clk
10ns
20ns
30ns
40ns
5
t3 mem_cs mem_rw t3 mem_a mem_bws
address valid
t4
t4
"11" t6 t1 t2
mem_d
data valid t6 t1 t2
mem_par
parity valid
Figure 62 - Flowthrough ZBT External Memory Timing - Read Access
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0ns mem_clk t3 mem_cs t3 mem_rw t3 mem_a t3 mem_bws "11" t3 t5 mem_d data valid t3 t5 mem_par parity valid t4 data valid t4 t6 "00" t6
address valid
Data Sheet
20ns 30ns 4
10ns
t4
t4
t4
t4 "11"
Figure 63 - Flowthrough SSRAM External Memory Timing - Write Access
0ns mem_clk
10ns
20ns
30ns
40ns
5
t3 mem_cs mem_rw t3 mem_a mem_bws
address valid
t4
t4
"11" t6 t1 t2
mem_d
data valid t6 t1 t2
mem_par
parity valid
Figure 64 - Flowthrough SSRAM External Memory Timing - Read Access
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0ns mem_clk t3 mem_cs t3 mem_rw t3 mem_a t3 mem_bws "11" "00" t3 t5 mem_d
data valid
address valid
Data Sheet
30ns 40ns 5
10ns
20ns
t4
t4
t4
t4 "11" t6 t4 data valid t4 t6 parity valid
t3 t5 mem_par
Figure 65 - Late-write External Memory Timing - Write Access
0ns mem_clk
10ns
20ns
30ns
40ns
50ns
6
t3 mem_cs mem_rw t3 mem_a mem_bws
address valid
t4
t4
"11" t6 t1 t2
mem_d
data valid t6 t1 t2
mem_par
parity valid
Figure 66 - Late-write External Memory Timing - Read Access
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0ns mem_clk t3 mem_cs t3 mem_rw t3 mem_a t3 mem_bws "11" "00" t3 t5 mem_d
data valid
address valid
Data Sheet
30ns 40ns 50ns 6
10ns
20ns
t4
t4
t4
t4 "11" t6 t4 data valid t4 t6 parity valid
t3 t5 mem_par
Figure 67 - Pipelined ZBT External Memory Timing - Write Access
0ns mem_clk
10ns
20ns
30ns
40ns
50ns
6
t3 mem_cs mem_rw t3 mem_a mem_bws
address valid
t4
t4
"11" t6 t1 t2
mem_d
data valid t6 t1 t2
mem_par
parity valid
Figure 68 - Pipelined ZBT External Memory Timing - Read Access
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0ns mem_clk t3 mem_cs t3 mem_rw t3 mem_a t3 mem_bws "11" t3 t5 mem_d data valid t3 t5 mem_par parity valid t4 data valid t4 t6 "00" t6
address valid
Data Sheet
20ns 30ns 4
10ns
t4
t4
t4
t4 "11"
Figure 69 - Pipelined External Memory Timing - Write Access
0ns mem_clk
10ns
20ns
30ns
40ns
50ns
6
t3 mem_cs mem_rw t3 mem_a mem_bws
address valid
t4
t4
"11" t6 t1 t2
mem_d
data valid t6 t1 t2
mem_par
parity valid
Figure 70 - Pipelined External Memory Timing - Read Access
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Characteristics 1 2 3 4 3s 4s 5 6 Input setup time Input hold time Clock to data valid Clock to data change Clock to data valid Clock to data change Clock rising to signal driven Clock rising to signal tri-state Symbol t1 t2 t3 t4 t3 t4 t5 t6 2 2 10 2 7 Min. 2 0 8.30 Typ. Max. Units ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
Primetime tested (load = 50 pf) Primetime tested (load = 50 pf) Spice tested with 2 memory chips Spice tested with 2 memory chips
Table 302 - Memory Interface Timing
9.4
H.100/H.110 Interface Timing
H.100 Input Sampling t3 t4
t5 t6
ct_c cd d (1/2 cycle) cd_d (3/4 cycle) cd d (4/4 cycle) t t2 H.100 t1 t1 ct_c t1
cd_d (end of Time-Slot; early tri-state) cd_d (middle of Time-Slot) cd_d (beginning of Time-Slot) t1 H.100 Frame t2 ct_c8 ct_frame t2 t1 X
Figure 71 - H.100 Input, Output, and Frame Sampling
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H.100 Message Channel Clock t30 ct_c8 ct_frame mc_clock t31
Data Sheet
H.100 Message Transmission Delay t40 t41 mc_t ct_mc
H.100 Message Reception Delay t50 ct_mc mc_rx
Figure 72 - H.100 Message Channel Clock, Transmission Delay, and Reception Delay
Figure 73 - H.100 Clock Skew (when chip is Master)
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Symbol t1 t2 t3 t4 t5 t6 t10 t11 t12 t13 t14 t20 t21 t30 t31 t40 t41 t50 t60 Description ct_c8 rise to ct_d valid ct_c8 rise to ct_d invalid ct_d valid to ct_c8 fall ct_c8 fall to ct_d invalid ct_d valid to ct_c8 rise ct_c8 rise to ct_d invalid ct_c8 rise to ct_d tri-state ct_c8 rise to ct_d invalid ct_c8 rise to ct_d invalid ct_c8 rise to ct_d driven ct_c8 rise to ct_d valid ct_frame valid to ct_c8 rise ct_c8 rise to ct_frame invalid ct_c8 rise to mc_clock rise ct_c8 fall to mc_clock fall mc_tx fall to ct_mc low mc_tx rise to ct_mc tri-state ct_mc fall to mc_rx fall ct_c8_a, ct_c8_b, ct_frame_a, ct_frame_b, c2, c4, sclk, sclkx2, frcomp, c16+, c16- maximum skew when generated by the chip Table 303 - H.100/H.110 Interface Timing 3 3 3 5 5 15 15 15 15 15 5 102 2 2 22 102 3 1 5 0 122 Min. Typical Max. 69
Data Sheet
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200 pf 200 pf 200 pf 200 pf 200 pf 200 pf 200 pf 200 pf Notes
9.5
H.100/H.110 Clocking Signals
The MT90503's H.100/H.110 interface generates all of the following signals with the specified timing.
125 uS /CT_FRAME
CT_C8
CT_Dx
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
Time Slot
0
127
Figure 74 - H.100/H.110 Clocking Signals
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Data Sheet
/CT_FRAME(A/B) CT_C8(A/B) /FR_COMP /C16 C2 /C4 SCLK
(2.048MHz)
SCLKx2*
(2.048MHz)
SCLK
(4.096MHz)
SCLKx2*
(4.096MHz) (8.192MHz)
SCLK
SCLKx2*
(8.192MHz)
Figure 75 - TDM Bus Timing - Compatibility Clock Generation
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1 Bit Cell
Tfs Tfh
Data Sheet
/CT_FRAME
Tfp Tc8h Tc8l
2.0V 0.6V
2.0V
CT_C8
0.6V Tc8p Tzdo Tdod 2.4V
Data Out
Ts 127
Bit 8
Tdoz Tdv
Ts 0
Bit 1
0.4V
Data In
Tdiv Tsamp
1.4V
Figure 76 - TDM Data Bus Timings
Symbol Tc8p Tc8h Tc8l Tsamp Tdoz Tzdo Tdod Tdv Tdiv Tfp Tfs Tfh F
Parameter Clock edge rate (All Clocks) Clock CT_C8 Period Clock CT_C8 High Time Clock CT_C8 Low Time Data Sample Point Data Output to HiZ Time Data HiZ to Output Time Data Output Delay Time Data Valid Time Data Invalid Time /CT_FRAME Width /CT_FRAME Setup Time /CT_FRAME Hold Time Phase Correction
Min. 0.25 122.066-F 49-F 49-F
Typ.
Max. 2 122.074+F 73+F 73+F
Units V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns
90 -20 0 0 0 102 90 45 45 0 122 0 22 22 69 112 180 90 90 10
Table 304 - H.100/H.110 Clocking Signals
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10.0 Glossary of Terms
Data Sheet
AAL0: ATM Adaptation Layer 0. AAL0 is a straight packaging of 48 bytes of data within an ATM cell. AAL0 can be used to treat either data cells (managed by CPU) or CBR cells (managed by TX/RX SAR). AAL1: ATM Adaptation Layer 1. AAL1 is used to transport constant bit rate (CBR) data on ATM. The main features of AAL1 are a cell sequence number that allows the detection of lost cells and a p-byte that allows reconverging of multi-channel VCs. AAL5: ATM Adaptation Layer 5. The main feature of AAL5 is a 32-bit CRC at the end of the cell that allows the detection and correction of errors in the data payload. In this design, AAL5 cells are used uniquely to treat CBR information. ATM: Asynchronous Transfer Mode. ATM is a networking standard based on 53-byte cells and is capable of carrying voice, data and video information simultaneously. CAS: Channel Associated Signalling. Signalling bits used to indicate the state of the channel. CBR: Constant Bit Rate. Cells in CBR format are sent out at a regular rate. CBR is applicable to voice channels. CDV: Cell Delay Variation. When cells arrive on a UTOPIA port, they arrive with a certain delay with respect to when they were sent. CDV is a measure of how much that delay varies on a VC. CLP: Cell Loss Priority. A 1-bit field in the ATM cell header that corresponds to the loss priority of a cell; cells with CLP = 1 can be discarded in a congestion situation. CNT: Counter. Events in the MT90503 will cause the counter to increment. CRC: Cyclic Redundancy Check. The CRC is a method of error detection and correction that is applied to a certain field of data. CRC is an efficient method of error detection because the odds of erroneously detecting a correct payload are low. DS1: Digital-Signal Level 1. DS1 is an electrical interface for digital transmissions that contains 24 64-Kbps channels. The physical interface defined to carry DS1 channels is T1. E1: E1 is the European equivalent of T1. They are similar with the main difference being E1 runs at 2.048 MHz instead of 1.544 Mbps, carrying 30 64kbps channels. ESF: Extended Super-Frame. ESF is a T1 format that defines multiframes as consisting of 24 frames, each one of which contains 1 byte per channel. FASTCAS: FASTCAS is not an acronym. It is capitalised in this document because it is a reserved word. FASTCAS means that multiframe integrity is not respected between the TDM and ATM buses. The TDM data is processed as soon as it is received, while CAS is sent when it is available. FIFO: First In, First Out. A FIFO memory is one in which the first byte to have been written into the memory is the first one to be read from the read port. GFC: Generic Flow Control. The GFC field is kept in the 4 highest bits of an ATM cell's header and is used for local functions (not carried end-to-end). The default value is "0000", meaning that GFC protocol is not enforced. GPI: General Purpose Input GPI/O: General Purpose Input or Output H.100/H.110: A TDM bus standard developed by ECTF to provide backward compatibility to existing TDM buses with more bandwidth and potential for development. HEC: Header Error Check. Using the fifth octet in the ATM cell header, ATM equipment may check for an error and correct the contents of the header. A CRC algorithm allows for single-error correction and multiple-error detection.
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Data Sheet
IE: Interrupt Enable. This is a register bit that enables a status event to generate an interrupt. This bit is always active-high. ISR: Interrupt Service Routine JTAG: Joint Test Action Group. LUT: Look-Up Table. In the UTOPIA module of the MT90503, the LUT is used to associate the data from received cells with the proper TDM output channels. The LUT is contained in the external memory. MFS: Multi-Frame Support. The MT90503 is capable of supporting the multi-frame standards of E1 and T1. MVIP: Multi-Vendor Integration Protocol. MVIP is a standard for transmitting data on a TDM bus. NNI: Network-Node Interface. NNI ATM cells do not have a GFC nibble, instead having an extra nibble of VPI. OAM: Operations Administration and Maintenance. MSB within the PTI field of the ATM cell header which indicates if the ATM cell carries management information such as fault indications. OC-3: Optical Carrier level-3. A Sonet channel that carries a bandwidth of 155.55 Mbps. OC-12: Optical Carrier level-12. A Sonet channel that carries a bandwidth of 622.08 Mbps. PC: Process Control bit. This is a register bit type that is written to `1' to initiate a hardware process. When the process completes, the hardware clears the bit. PCM: Pulse Code Modulation. PCM is the basic method of encoding an analog voice signal into digital form. PHY: PHYsical layer. The bottom layer of the ATM Reference Model, it provides ATM cell transmission over the physical interfaces that interconnect the various ATM devices. PLL: Phase Lock Loop. A phase lock loop is a component that generates an output clock by synchronising itself to an input clock. PLLs are often used to multiply the frequency of clocks. PTI: Payload Type Identifier. The PTI field is a 3-bit header field that encodes various cell management information. Bit 2 (MSB) indicates OAM information or user data, bit 1 is Explicit Forward Congestion Control Indication (whether the cell may have been delayed by network congestion -- never examined by the MT90503) and bit 0 (LSB) indicates that a CBR-AAL5 cell is the final cell in a frame. PUL: PULse bit. This is a register bit that is written to `1' to indicate an event to the hardware. This bit is always read at `0'. RAM: Random Access Memory. RAM is the main memory in the computer. It is called "random" because any random address can be accessed in an equal amount of time. RO: Read Only. This serves to define registers that cannot be written to by the CPU. ROL: Read Only Latch. This defines status bits. Status bits cannot be written to `1' by the CPU; however, once the status bit is set, the CPU can clear it by writing a `0' over it. RW: Read Write. This type of register bit will be readable and writeable by the CPU. SAR: Segmentation And Reassembly. Method of partitioning, at the source, frames into ATM cells and reassembling, at the destination, these cells back into information frames; lower sublayer of the AAL which inserts data from the information frames into cells and then adds the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the ATM layer. SCSA: Signal Computing System Architecture SRTS: Synchronous Residual Time Stamp. SRTS is a clock recovery technique, which transmits timing information over the network to allow the source clock to be reconstructed at the other end. SRTS is sent in a 4-bit value transmitted over 8 AAL1 cells.
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D1
DIMENSION
E2
E
E1
D/4
E/4
MIN MAX A 2.11 2.56 A1 0.50 0.70 A2 1.10 1.25 40.20 D 39.80 D1 35.56 REF D2 37.50 39.50 E 40.20 39.80 E1 35.56 REF E2 39.50 37.50 b 0.60 0.90 e 1.27 N 503 Conforms to JEDEC MS - 034
D2
e
D
A2
NOTE:
b
A1 A
1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM REF
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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